RCM_SRS0 field descriptions (continued)
Field
Description
1
LVD
Low-Voltage Detect Reset
If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset occurs. This bit is
also set by POR.
0
Reset not caused by LVD trip or POR
1
Reset caused by LVD trip or POR
0
WAKEUP
Low Leakage Wakeup Reset
Indicates a reset has been caused by an enabled wakeup source while the chip was in a low leakage
mode. Any enabled wakeup source in a VLLSx mode causes a reset. This bit is cleared by any reset
except WAKEUP.
0
Reset not caused by wakeup source
1
Reset caused by wakeup source
15.2.2 System Reset Status Register 1 (RCM_SRS1)
This register includes read-only status flags to indicate the source of the most recent
reset. The reset state of these bits depends on what caused the MCU to reset.
NOTE
The reset value of this register depends on the reset source:
• POR (including LVD) — 0x00
• LVD (without POR) — 0x00
• VLLS mode wakeup — 0x00
• Other reset — a bit is set if its corresponding reset source
caused the reset
Address: 4007_F000h base + 1h offset = 4007_F001h
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
RCM_SRS1 field descriptions
Field
Description
7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
6
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
5
SACKERR
Stop Mode Acknowledge Error Reset
Table continues on the next page...
Chapter 15 Reset Control Module (RCM)
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
Freescale Semiconductor, Inc.
191
Содержание KKL02Z32CAF4R
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