Freescale Semiconductor HCS08 Series, Справочное руководство

Страница: 194 / 306

16-Bit Serial Peripheral Interface (S08SPI16V1)
MC9S08JS16 MCU Series Reference Manual, Rev. 4
194 Freescale Semiconductor
7 6 5 4 3 2 1 0
R
SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
W
Reset 0 0 0 0 0 1 0 0
Figure 13-5. SPI Control Register 1 (SPIC1)
Table 13-1. SPIC1 Field Descriptions
Field Description
7
SPIE
SPI Interrupt Enable (for SPRF and MODF) — This is the interrupt enable for SPI receive buffer full (SPRF)
and mode fault (MODF) events.
0 Interrupts from SPRF and MODF inhibited (use polling)
1 When SPRF or MODF is 1, request a hardware interrupt
6
SPE
SPI System Enable — This bit enables the SPI system and dedicates the SPI port pins to SPI system functions.
If SPE is cleared, SPI is disabled and forced into idle state, and all status bits in the SPIS register are reset.
0 SPI system inactive
1 SPI system enabled
5
SPTIE
SPI Transmit Interrupt Enable — This is the interrupt enable bit for SPI transmit buffer empty (SPTEF).
0 Interrupts from SPTEF inhibited (use polling)
1 When SPTEF is 1, hardware interrupt requested
4
MSTR
Master/Slave Mode Select — This bit selects master or slave mode operation.
0 SPI module configured as a slave SPI device
1 SPI module configured as a master SPI device
3
CPOL
Clock Polarity — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI modules,
the SPI modules must have identical CPOL values.
This bit effectively places an inverter in series with the clock signal from a master SPI or to a slave SPI device.
Refer to
Section 13.4.5, “SPI Clock Formats ” for more details.
0 Active-high SPI clock (idles low)
1 Active-low SPI clock (idles high)
2
CPHA
Clock Phase — This bit selects one of two clock formats for different kinds of synchronous serial peripheral
devices. Refer to Section 13.4.5, “SPI Clock Formats ” for more details.
0 First edge on SPSCK occurs at the middle of the first cycle of a data transfer
1 First edge on SPSCK occurs at the start of the first cycle of a data transfer
1
SSOE
Slave Select Output Enable — This bit is used in combination with the mode fault enable (MODFEN) bit in
SPIC2 and the master/slave (MSTR) control bit to determine the function of the SS pin as shown in Table 13-2 .
0
LSBFE
LSB First (Shifter Direction) — This bit does not affect the position of the MSB and LSB in the data register.
Reads and writes of the data register always have the MSB in bit 7 (or bit 15 in 16-bit mode).
0 SPI serial data transfers start with most significant bit
1 SPI serial data transfers start with least significant bit
Table 13-2. SS Pin Function
MODFEN SSOE Master Mode Slave Mode
0 0 General-purpose I/O (not SPI) Slave select input
0 1 General-purpose I/O (not SPI) Slave select input
1 0 SS input for mode fault Slave select input
1 1 Automatic SS output Slave select input