Register Model
e200z3 Power Architecture Core Reference Manual, Rev. 2
Freescale Semiconductor
2-23
SPR numbers corresponding to IVOR16–IVOR31 are reserved. IVOR32–IVOR47 and IVOR60–IVOR63
are reserved. SPR numbers for IVOR32–IVOR63 are allocated for implementation-dependent use
(IVOR32–IVOR34 (SPR 528–530) are defined by the EIS). IVOR assignments are shown in
2.9
Exception Syndrome Register (ESR)
The ESR, shown in
, provides a syndrome to distinguish exceptions that can generate the same
interrupt type. The e200z3 adds implementation-specific bits to this register.
Table 2-12. IVOR Assignments
IVOR Number
SPR
Interrupt Type
IVOR0
400 Critical input
IVOR1
401 Machine check
IVOR2
402 Data storage
IVOR3
403 Instruction storage
IVOR4
404 External input
IVOR5
405 Alignment
IVOR6
406 Program
IVOR7
407 Floating-point unavailable
IVOR8
408 System call
IVOR9
409 Auxiliary processor unavailable. (Defined by the EIS but not supported in the e200z3.)
IVOR10
410 Decrementer
IVOR11
411 Fixed-interval timer interrupt
IVOR12
412 Watchdog timer interrupt
IVOR13
413 Data TLB error
IVOR14
414 Instruction TLB error
IVOR15
415 Debug
IVOR16–IVOR31
—
Reserved for future architectural use
IVOR32
528 SPE APU unavailable (EIS–defined)
IVOR33
529 SPE floating-point data exception (EIS–defined)
IVOR34
530 SPE floating-point round exception (EIS–defined)
IVOR35–IVOR63
—
Allocated for implementation-dependent use
Содержание e200z3
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