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External Core Complex Interfaces
e200z3 Power Architecture Core Reference Manual, Rev. 2
7-24 Freescale Semiconductor
Table 7-19 describes debug/emulation (Nexus 1/ OnCE) support signals.
Table 7-19. Descriptions of Debug/Emulation (Nexus 1/ OnCE) Support Signals
Signal I/O Signal Description
jd_en_once I OnCE enable. Enables the OnCE controller to allow certain instructions and operations to be executed.
Other systems should tie this signal asserted to enable full OnCE operation.
j_en_once_regsel and j_key_in
are provided to assist external logic performing security checks.
State
Meaning
Asserted—Enables the full OnCE command set, as well as operation of control signals and
OnCE control register functions.
Negated—Only the bypass, ID, and Enable_OnCE commands are executed by the OnCE unit;
all other commands default to a bypass command. The OnCE status register (OSR) is not
visible when OnCE operation is disabled. In addition, OCR functions and the operation of
jd_de_b are disabled. Secure systems may leave this signal negated until a security check
is performed.
Timing Must change state only during the test-logic-reset, run-test/idle, or update_dr TAP states. A new
value takes effect after one additional
j_tclk cycle of synchronization.
jd_debug_b O Debug session. A debug session includes single-step operations (Go+NoExit OnCE commands). This
signal is provided to inform system resources that access is occurring for debug purposes, thus allowing
certain resource side effects to be frozen or otherwise controlled. Examples may include FIFO state change
control and control of side-effects of register or memory accesses. See
Section 9.5.4, “OnCE Interface
Signals.”
State
Meaning
Asserted—Asserted when the processor enters debug mode. It remains asserted for the duration
of a debug session. that is, during OnCE single-step executions.
jd_de_b I Debug request. Normally the input from the top-level DE_b open-drain bidirectional I/O cell. See
Section 9.5.4, “OnCE Interface Signals.”
State
Meaning
Asserted—A debug request is pending.
Negated—No debug request is pending.
Timing Assertion—Not internally synchronized by the core and must meet setup and hold time
constraints relative to j_tclk. To be recognized, it must be held asserted for a minimum of
two j_tclk periods, and jd_en_once must be in the asserted state. jd_de_b is synchronized
to m_clk in the debug module before being sent to the processor (two clocks).
jd_de_en O DE_b active high output enable. Enable for the top-level DE_b open-drain bidirectional I/O cell. See
Section 9.5.4, “OnCE Interface Signals.”
State
Meaning
Asserted—the top-level DE_b open-drain bidirectional I/O cell is enabled.
Negated—the top-level DE_b open-drain bidirectional I/O cell is disabled.
Timing Assertion—Asserted for three
j_tclk periods upon processor entry into debug mode.
jd_mclk_on
I Processor clock on. Driven by system-level clock control logic to indicate the
m_clk input state
State
Meaning
Asserted—The processor’s
m_clk input is active.
Negated—The processor’s m_clk input is not active.
Timing Assertion—Synchronized to j_tclk and provided as an OSR status bit.
jd_watchpoint
[0:7]
O Watchpoint events. Indicate whether a watchpoint occurred. Each debug address compare function
(IAC1–IAC4, DAC1–DAC2), and debug counter event (DCNT1–DCNT2) is capable of triggering a
watchpoint output.
State
Meaning
Asserted—A watchpoint occurred
Negated—No watchpoint occurred