Freescale Semiconductor e200z3, Справочное руководство

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Instruction Pipeline and Execution Timing
e200z3 Power Architecture Core Reference Manual, Rev. 2
6-16 Freescale Semiconductor
Figure 6-19 shows timing for interrupt recognition and exception processing overhead. This example
shows best-case response timing when an interrupt is received and processed during execution of a
multicycle interruptible instruction.
Figure 6-19. Interrupt Recognition and Handler Instruction Execution—Multi-Cycle
Instruction Abort
6.7 Instruction Timings
Table 6-2 shows instruction timing for various instruction classes. Pipelined instructions are shown with
cycles of total latency and throughput. Divide instructions are not pipelined and block other instructions
from executing during divide execution.
Load/store multiple instruction cycles are represented as a fixed number of cycles plus a variable number
of cycles where ‘n’ is the number of words accessed by the instruction. Additionally, cycle times marked
with an ampersand (&) require additional cycles due to serialization.
Time Slot
Next Instruction
IFETCH EXE Abort DEC -- --
Multi-Cycle
Interruptible
IFETCH Abort -- DEC --
1 2 3 4 5 6 7 8 9 10
p_extint_b
Final Sample Point
p_iack
IFETCH EXE WB DEC First Instruction of Handler
ec_excp_detected*
oldpc_->srr0*
oldmsr_->srr1*
update_esr*
update_msr*
* Internal Operations
Instruction