Memory Management Unit
e200z3 Power Architecture Core Reference Manual, Rev. 2
Freescale Semiconductor
5-11
The supervisor instructions tlbre, tlbwe, tlbsx, tlbivax, and tlbsync are fully described in the EREF.
•
TLB Read Entry (tlbre)—Causes contents of the TLB entry specified by MAS0[TLBSEL,ESEL])
to be placed into MAS1–MAS3.
describes how MAS fields are updated.
•
TLB Write Entry (tlbwe)—Causes the contents of certain fields within the MAS1, MAS2, and
MAS3 to be written into the TLB entry specified by MAS0[TLBSEL,ESEL].
describes
how MAS fields are updated.
•
TLB Search Indexed (tlbsx)—Updates the MAS registers conditionally based on success or failure
of a TLB lookup. The lookup is controlled by an effective address provided by rB as specified in
the instruction encoding, and by MAS6[SAS,SPID]. The values placed into MAS0–MAS3 differ
depending on the success of the search.
describes how MAS fields are updated.
•
TLB Invalidate (tlbivax)—Invalidates TLB entries that correspond to the virtual address
calculated by this instruction. The address is detailed in
. No other information except for
that shown in
is used for the invalidation (AS and TID values are ignored).
Additional information about the targeted TLB entries is encoded in two of the lower bits of the
effective address calculated by the tlbivax.
EA[0–19] are used to perform the tlbivax invalidation of TLB1.
t
•
TLB Synchronize (tlbsync)—Treated as a privileged no-op by the e200z3.
5.5
TLB Operations
This section describes how the software (with some hardware assistance) maintains TLB1.
5.5.1
Translation Reload
The TLB reload function is performed in software with some hardware assistance. This hardware
assistance consists of the following:
•
Five 32-bit MMU assist registers (MAS0–MAS4, MAS6) for support of the tlbre, tlbwe, and tlbsx
TLB management instructions.
•
Loading of MAS0–MAS2 based upon defaults in MAS4 for TLB miss exceptions. This
automatically generates most of the TLB entry.
Table 5-4. tlbivax EA Bit Definitions
Bits
Field
0–19
EA[0–19]
20–27 Reserved
1
1
These bits should be zero for future compatibility. They are ignored.
28
TLBSEL (1 = TLB1). Should be set, for future compatibility and to ensure that TLB1 is targeted by the invalidate.
29
INV_ALL. If set, indicates that the invalidate operation needs to completely invalidate all TLB1 entries that are not
marked as invalidation protected (IPROT = 1)
30–31 Reserved
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