Interrupts and Exceptions
e200z3 Power Architecture Core Reference Manual, Rev. 2
4-20
Freescale Semiconductor
4.6.13
Watchdog Timer Interrupt (IVOR12)
The e200z3 implements the watchdog timer interrupt as defined in Book E. The exception is triggered by
the first enabled watchdog timeout.
A watchdog timer interrupt occurs when no higher priority exception exists, a watchdog timer exception
exists (TSR[WIS]=1), and the interrupt is enabled (both TCR[WIE] and MSR[CE] = 1).
The TSR holds the watchdog interrupt bit set by the timer facility when an exception is detected. Software
must clear this bit in the interrupt handler to avoid repeated watchdog interrupts.
lists register settings when a watchdog timer interrupt is taken.
MSR
UCLE 0
SPE 0
WE
0
CE
—
EE
0
PR
0
FP
0
ME
—
FE0
0
DE
—
FE1
0
IS
0
DS
0
RI
—
ESR
Unchanged
MCSR
Unchanged
DEAR
Unchanged
Vector
IVPR[32–47] || IVOR11[48–59] || 0b0000
Table 4-21. Watchdog Timer Interrupt Register Settings
Register
Setting Description
CSRR0
Set to the effective address of the instruction that the processor would have attempted to execute next
if no exception conditions were present.
CSRR1
Set to the contents of the MSR at the time of the interrupt
MSR
UCLE 0
SPE
0
WE
0
CE
0
EE
0
PR
0
FP
0
ME
—
FE0
0
DE
0/—
1
FE1
0
IS
0
DS
0
RI
0
2
1
DE is cleared when the debug APU is disabled. Clearing of DE is optionally supported by control in HID0
when the debug APU is enabled.
2
RI is cleared by all critical class interrupts using CSRR0/1 and machine check interrupts. These interrupt
handlers should set RI early in the handler after CSRR0/1 have been saved for improved recoverability.
ESR
Unchanged
MCSR
Unchanged
DEAR
Unchanged
Vector
IVPR[32–47] || IVOR12[48–59] || 0b0000
Table 4-20. Fixed-Interval Timer Interrupt Register Settings (continued)
Register
Setting Description
Содержание e200z3
Страница 1: ...e200z3 Power Architecture Core Reference Manual Supports e200z3 e200z335 e200z3coreRM Rev 2 06 2008 ...
Страница 32: ...e200z3 Power Architecture Core Reference Manual Rev 2 xii Freescale Semiconductor ...
Страница 50: ...Register Model e200z3 Power Architecture Core Reference Manual Rev 2 2 2 Freescale Semiconductor ...
Страница 238: ...Memory Management Unit e200z3 Power Architecture Core Reference Manual Rev 2 5 16 Freescale Semiconductor ...
Страница 332: ...Power Management e200z3 Power Architecture Core Reference Manual Rev 2 8 4 Freescale Semiconductor ...
Страница 424: ...Revision History e200z3 Power Architecture Core Reference Manual Rev 2 A 2 Freescale Semiconductor ...