Freescale Semiconductor e200z3, Справочное руководство

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Register Model
e200z3 Power Architecture Core Reference Manual, Rev. 2
2-74 Freescale Semiconductor
2.18.4 Reset Settings
Table 2-41 shows the state of the PowerPC Book E registers and other optional resources immediately
following a system reset.
SPRG5 SPR general 5 261 Read only No No
277 R/W Yes No
SPRG6 SPR general 6 262 Read only No No
278 R/W Yes No
SPRG7 SPR general 7 263 Read only No No
279 R/W Yes No
SRR0 Save/restore register 0 26 R/W Yes No
SRR1 Save/restore register 1 27 R/W Yes No
SVR System version register 1023 Read only Yes Yes
TBL Time base lower 268 Read only No No
284 Write only Yes No
TBU Time base upper 269 Read only No No
285 Write only Yes No
TCR Timer control register 340 R/W Yes No
TLB0CFG TLB0 configuration register 688 Read only Yes Yes
TLB1CFG TLB1 configuration register 689 Read only Yes Yes
TSR Timer status register 336 Read/Clear
4
Yes No
USPRG0 User SPR general 0 256 R/W No No
XER Integer exception register 1 R/W No No
Notes:
1
Only writable when multiple contexts are implemented. Otherwise, writes are ignored
2
The debug status register (DBSR) is read using mfspr . DBSR cannot be directly written. Instead, DBSR bits corresponding
to 1 bits in the GPR can be cleared using mtspr .
3
IVOR9 handles the auxiliary processor unavailable interrupt. This interrupt is defined by the EIS but not supported in the
e200z3; therefore, use of IVOR9 is not supported in the e200z3.
4
TSR is read using mfspr , but it cannot be directly written. Instead, TSR bits corresponding to 1 bits in the GPR can be cleared
using mtspr .
Table 2-41. Reset Settings for e200z3 Resources
Resource System Reset Setting
Program counter p_rstbase[0:19] || 0xFFC
GPRs Unaffected
1
Table 2-40. Special-Purpose Registers (continued)
Mnemonic Name SPR Number Access Privileged e200z3-Specific