Freescale Semiconductor e200z3, Справочное руководство

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Register Model
e200z3 Power Architecture Core Reference Manual, Rev. 2
Freescale Semiconductor 2-65
2.16.4 MMU Assist Registers (MAS0–MAS4, MAS6)
The e200z3 uses six special-purpose registers (MAS0–MAS4, and MAS6) for reading, writing, and
searching the TLBs. The MAS registers can be read or written using the mfspr and mtspr instructions.
The e200z3 does not implement the MAS5 register, which is present in other Freescale Book E designs,
because the tlbsx instruction only searches based on a single SPID value.
For details on the MASn registers, see Section 5.6.5, “MMU Assist Registers (MAS).” The MAS0 register
is shown in Figure 2-47 .
MAS0 fields are defined in Table 2-32 .
The MAS1 register is shown in Figure 2-48 .
32 33 34 35 36 42 43 47 48 58 59 60 63
Field — TLBSEL — ESEL — NV
Reset Undefined on m_por assertion, unchanged on p_reset_b assertion
R/W R/W
SPR SPR 624
Figure 2-47. MAS Register 0 (MAS0) Format
Table 2-32. MAS0—MMU Read/Write and Replacement Control
Bits Name Description
32–33 — Reserved, should be cleared.
34–35 TLBSEL Selects TLB for access.
01 TLB1 (ignored by the e200z3, should be written to 01 for future compatibility).
36–42 — Reserved, should be cleared.
43–47 ESEL Entry select for TLB1.
Bit 43 is reserved on e200z335, so ESEL includes only bits 44–47 for e200z335.
48–59 — Reserved, should be cleared.
60–63 NV Next replacement victim for TLB1 (software managed). Software updates this field; it is copied to the ESEL
field on a TLB error (See
Table 5-6 ).
Bit 60 is reserved on e200z335, so NV includes only bits 61–63 for e200z335.
32 33 34 39 40 47 48 50 51 52 55 56 63
Field VALID IPROT — TID — TS TSIZE —
Reset Undefined on m_por assertion, unchanged on p_reset_b assertion
R/W R/W
SPR SPR 625
Figure 2-48. MMU Assist Register 1 (MAS1)