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External Interrupts

Technical Summary, Rev. 3

Freescale Semiconductor

2-13

2.9   External Interrupts

Two on-board push-button switches are provided for external interrupt generation, as shown in 

Figure 2-8

. S1 allows the user to generate a hardware interrupt for signal line IRQA. S2 allows 

the user to generate a hardware interrupt for signal line IRQB. These two switches allow the user 
to generate interrupts for his user-specific programs.

56852

IRQA

IRQB

+3.3V

+3.3V

10K

10K

S1

S2

0.1µF

0.1µF

Figure 2-8.   Schematic Diagram of the User Interrupt Interface

Содержание 56852

Страница 1: ...56F850 16 bit Digital Signal Controllers freescale com 56852 Evaluation Module User Manual DSP56852EVMUM Rev 3 07 2005...

Страница 2: ......

Страница 3: ...OM Data FLASH Memory 2 5 2 4 RS 232 Serial Communications 2 6 2 5 Clock Source 2 7 2 6 Operating Mode 2 8 2 7 Debug LEDs 2 8 2 8 Debug Support 2 9 2 8 1 JTAG Connector 2 10 2 8 2 Parallel JTAG Interfa...

Страница 4: ...DSP56852EVM User Manual Rev 3 ii Freescale Semiconductor Appendix A DSP56852EVM Schematics Appendix B DSP56852EVM Bill of Material...

Страница 5: ...ry Interface 2 4 2 3 SPI EEPROM Memory Block Diagram 2 5 2 4 Schematic Diagram of the RS 232 Interface 2 6 2 5 Schematic Diagram of the Clock Interface 2 7 2 6 Schematic Diagram of the Debug LED Inter...

Страница 6: ...DSP56852EVM User Manual Rev 3 iv Freescale Semiconductor...

Страница 7: ...ection 2 8 2 4 LED Control 2 8 2 5 JTAG Connector Description 2 10 2 6 Parallel JTAG Interface Disable Jumper Selection 2 10 2 7 Parallel JTAG Interface Connector Description 2 12 2 8 Codec Sample Rat...

Страница 8: ...DSP56852EVM User Manual Rev 3 vi Freescale Semiconductor...

Страница 9: ...is manual is organized into two chapters and two appendixes Chapter 1 Introduction provides an overview of the EVM and its features Chapter 2 Technical Summary describes in detail the 56852 hardware A...

Страница 10: ...d in most figures WE OE In schematic drawings Active Low Signals may be noted by a backslash WE Hexadecimal Values Begin with a sym bol 0FF0 80 Decimal Values No special symbol attached to the number...

Страница 11: ...mer to evaluate the silicon and develop his application GPIO General Purpose Input and Output port on Freescale s family of controllers does not share pin functionality with any other peripheral on th...

Страница 12: ...ale Semiconductor 2 DSP56852 Digital Signal Processor User s Manual Freescale Semiconductor 3 DSP56852 Digital Signal Processor Technical Data Freescale Semiconductor SPI Serial Peripheral Interface p...

Страница 13: ...M run it and debug it using a debugger via the JTAG Enhanced OnCE EOnCE port The breakpoint features of the EOnCE port enable the user to easily specify complex break conditions and to execute user de...

Страница 14: ...ghter Card Connector RESET LOGIC MODE LOGIC CS0 Program Memory 128Kx16 bit SRAM Memory Daughter Card Connector JTAG Connector Parallel JTAG Interface 4 00MHz Crystal DSub 25 Pin CS1 CS2 Data Memory 12...

Страница 15: ...6F801EVM Default Jumper Options Jumper Group Comment Jumpers Connections JG1 Enable on board Byte selectable SRAM via CS1 CS2 U3 1 2 3 4 JG2 Enable on board Word selectable SRAM via CS0 U2 1 2 JG3 Use...

Страница 16: ...e parallel extension cable to the Parallel port of the host computer 2 Connect the other end of the parallel extension cable to P1 shown in Figure 1 3 on the 56F801EVM board This provides the connecti...

Страница 17: ...ng the architecture and instruction set of the 56852 processor The main features of the 56852EVM with board and schematic reference designators include 56852 16 bit 1 8V 3 3V Digital Signal Processor...

Страница 18: ...0 part designated as U1 on the board and in the schematics This part will operate at a maximum speed of 120MHz A full description of the 56852 including functionality and user information is provided...

Страница 19: ...ny modulo address space This memory bank will operate with one wait state access while the 56852 is running at 120MHz and can be disabled by removing the jumper at JG2 56852 GS72116 A0 A16 D0 D15 RD W...

Страница 20: ...while the 56852 is running at 120MHz and can be disabled by removing the jumpers at JG1 56852 GS72116 A0 A16 D0 D15 RD WR A0 A16 DQ0 DQ15 OE WE CE JG1 Jumper Pin 1 2 Enable SRAM Low Byte Jumper Pin 3...

Страница 21: ...ck JG6 is provided to allow the user to disconnect the on board SPI EEPROM Data FLASH from the SPI port and allow him to connect his own SPI port peripheral Since the SPI port and ISSI port are multip...

Страница 22: ...r P6 Flow control is not provided but could be implemented using uncommitted GPIO signals The pinout of connector P6 is listed in Table 2 2 The RS 232 level converter transceiver can be disabled by pl...

Страница 23: ...nd JG4 see Figure 2 5 If the input frequency is above 4MHz then the EXTAL input should be jumpered to ground by adding a jumper between JG4 pins 1 and 2 The input frequency would then be injected on J...

Страница 24: ...from External byte wide memory 1 3 4 5 6 Bootstrap from SPI 2 1 2 5 6 Normal Expanded mode 3 5 6 Development Expanded mode 2 7 Debug LEDs Six on board Light Emitting Diodes LEDs are provided to allow...

Страница 25: ...6 Schematic Diagram of the Debug LED Interface 2 8 Debug Support The 56852EVM provides an on board Parallel JTAG Host Target Interface and a JTAG interface connector for external Target Interface supp...

Страница 26: ...debugger program Table 2 5 shows the pin out for this connector Table 2 5 JTAG Connector Description J3 Pin Signal Pin Signal 1 TDI 2 GND 3 TDO 4 GND 5 TCK 6 GND 7 NC 8 KEY 9 RESET 10 TMS 11 3 3V 12...

Страница 27: ...d programs and work with the 56852 s registers Table 2 7 shows the pin out for this connector When using the parallel JTAG interface the jumper at JG7 should be removed as shown in Table 2 6 DB 25 Con...

Страница 28: ...NC 14 NC 2 PORT_RESET 15 PORT_IDENT 3 PORT_TMS 16 NC 4 PORT_TCK 17 NC 5 PORT_TDI 18 GND 6 PORT_TRST 19 GND 7 PORT_DE 20 GND 8 PORT_IDENT 21 GND 9 PORT_VCC 22 GND 10 NC 23 GND 11 PORT_TDO 24 GND 12 NC...

Страница 29: ...ion as shown in Figure 2 8 S1 allows the user to generate a hardware interrupt for signal line IRQA S2 allows the user to generate a hardware interrupt for signal line IRQB These two switches allow th...

Страница 30: ...an internal Power On RESET Additional reset logic is provided to support the RESET signals from the JTAG connector the Parallel JTAG Interface and the user RESET push button refer to Figure 2 9 RESET...

Страница 31: ...e power regulation on the 56852EVM provides 5 0V DC voltage regulation for the codec s analog circuits and to the additonal voltage regulation logic on the EVM The additonal voltage regulation logic p...

Страница 32: ...8 The codec supports 3 3V digital levels eliminating the need for voltage level translation circuitry Additionally a set of zero ohm resistors are provided on the EVM to allow a user to disconnect the...

Страница 33: ...s used for serial communication with the codec On the controller side the Serial Transmit Data pin STXD is an output when data is being transmitted to the codec The Serial Receive Data pin SRXD is an...

Страница 34: ...elected on the Sample Rate Selector switch S4 see Table 2 8 for selection options Codec control information is sent over a separate serial port using PC5 as the Control Chip Select signal CCS PE0 as t...

Страница 35: ...ns the controller s external memory bus signals The other connector J2 contains the controller s peripheral port signals 2 13 1 Memory Daughter Card Expansion Connector The controller s external memor...

Страница 36: ...23 D4 24 D11 25 D5 26 D12 27 D6 28 D13 29 A18 30 A17 31 D7 32 D14 33 CS0 34 D15 35 A0 36 RD 37 A1 38 A6 39 A16 40 GND 41 A2 42 A5 43 A3 44 A4 45 A19 CS3 46 CS2 47 3 3V 48 3 3V 49 GND 50 GND 51 5 0V Ta...

Страница 37: ...signal to pin assignments Table 2 12 Peripheral Daughter Card Connector Description J2 Pin Signal Pin Signal 1 CS0 PA0 2 CS1 PA1 3 A20 CLKO 4 CS2 PA2 5 A17 TIO0 6 A18 TIO1 7 GND 8 GND 9 GND 10 GND 11...

Страница 38: ...are located in corners of the board The 5 0VA and AGND test points are located in the analog corner of the board The 1 8V and 3 3V test points are located in the power supply section of the board 43...

Страница 39: ...DSP56852EVM Schematics Rev 3 Freescale Semiconductor Appendix A 1 Appendix A DSP56852EVM Schematics...

Страница 40: ...H 9 F 8 F 7 G 6 E 8 E 7 E 6 D 8 D 7 D 9 C 8 A 9 D 5 E 1 H 1 G 9 B 9 A 4 B 1 G 1 J 6 J 9 C 9 A 5 C 1 E 5 F 6 G 5 H 6 J 8 E 3 J 5 E 9 J 7 D 1 J 4 F 9 B 5 B 6 A 1 C 2 A 7 A 6 B 7 A 8 C 6 D 6 C 7 B 8 C 4...

Страница 41: ...480 413 2510 V C C 3 P O R M O D A M O D B M O D C D 1 3 D 1 4 D 1 5 V C C 2 P O R IRQA IRQB EXTAL XTAL D 1 3 D 1 4 D 1 5 1 2 2 8 8 M H Z 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V J G 4 1 2 3 Y 1 4 00MHz R 7 1 1...

Страница 42: ...D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 1 0 D 1 1 D 1 2 D 1 3 D 1 4 D 1 5 CS0 CS2 CS1 3 3V 3 3V 3 3V 3 3V U 2 G S 7 2 1 1 6 A T P 7 7 8 1 9 10 2 13 14 3 15 16 4 29 30 5 31 32 18 35 36 19 37 38 20 21 24 25 2...

Страница 43: ...4 Title Document Date Size Designer Sheet of Rev Number 480 413 5090 FAX 480 413 2510 R S T W P R S T W P E E _ S O E E _ S I E E _ S C K E E _ C S S S M I S O M O S I S C K 3 3V 3 3V R 5 8 1 0 K R 5...

Страница 44: ...2 I N R X T3IN TXD R X D 3 3V 3 3V 3 3V R 5 6 1 K R 5 7 1 K R 5 5 1 K R 5 4 1 K R 5 1 1 K R 5 0 1 K J G 8 1 2 R 5 2 1 K T5 1 T6 1 T7 1 T8 1 P 6 5 9 4 8 3 7 2 6 1 T3 1 T2 1 T1 1 T4 1 U 6 M A X 3 2 4 5...

Страница 45: ...D TXD 5 0VA 3 3V 3 3V 3 3V 3 3V 5 0VA R 2 0 5 62K 1 C 1 6 0 47uF R 2 7 3 9 2K 1 R 2 3 5 62K 1 C 1 8 0 47uF C 9 4 7 0pF R 2 5 5 62K 1 C 1 4 0 0022uF R 2 8 39 2K 1 C 1 3 0 33uF C 1 1 4 7 0pF C 1 5 0 002...

Страница 46: ..._ DE T C K TDI TMS DE TDI TDO TCK TMS RESET TRST P O R DE 3 3V 3 3V 3 3V 3 3V 3 3V R 1 0 51 Oh m R 1 4 5 1K R 1 3 5 1K J 3 1 3 5 7 9 1 1 1 3 2 4 6 8 1 0 1 2 1 4 R 1 5 47K R 1 7 47K R 4 270 R 6 270 R 5...

Страница 47: ...N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D G N D D 0 D 2 D 4 D 6 D 8 D 1 4 A 0 A 2 A 6 A 8 A 1 4 R D W R D 1 D 3 D 5 D 7 D 9 D 1 3 D 1 5 A 5 A 7 A 9 A 1 3 A 1 5 C S 0 A 1 C S 1 A...

Страница 48: ...13 2510 5 0V 5 0 V A 3 3V 3 3V V C C 1 8V 5 0V 5 0V C 2 0 1uF C 6 0 1uF U 7 M C 3 3 2 6 9 D T 3 3 3 2 4 1 V I N V O U T V O U T G N D L1 F E R R I T E B E A D L4 F E R R I T E B E A D L3 F E R R I T E...

Страница 49: ...413 5090 FAX 480 413 2510 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 1 8V 1 8V 1 8V 1 8V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 5 0 V A 3 3V 3 3V 5 0 V A 3 3V 1 8V 3 3V 3 3V C 4 1 0 01uF C 4 2 0 1...

Страница 50: ...DSP56852EVM User Manual Rev 3 Appendix A 12 Freescale Semiconductor...

Страница 51: ...1 3 3V Voltage Regulator U7 ON Semiconductor MC33269DT 3 3 1 1 8V Voltage Regulator U8 ON Semiconductor MC33269DT ADJ 1 74LCX244 U9 ON Semiconductor MC74LCX244ADW 1 74AC00 U10 Fairchild 74AC00SC 1 12...

Страница 52: ...SMEC RC73L2A39 2KOHMFT 13 1K R32 R33 R50 R57 R62 R63 R65 SMEC RC73L2A1KOHMJT 4 20 0K R37 R39 R42 R44 SMEC RC73L20 0KOHMFT 3 470K R41 R43 R86 SMEC RC73L2A470KOHMJT 0 10K R45 SMEC RC73L2A10KOHMJT 2 R66...

Страница 53: ...6 C18 SMEC MCCE474K3NR T1 12 0 01PF C33 C35 C37 C39 C41 C43 C45 C47 C49 C52 C55 C57 SMEC MCCE103K2NR T1 Jumpers 3 1 u 2 2mm Header JG2 JG7 JG8 SAMTEC TMM 102 02 S S 2 3 u 1 2mm Header JG3 JG4 SAMTEC T...

Страница 54: ...6 AMPHENOL 617 C009S AJ120 2 51 Pin HD Connector J1 J2 BERG 91930 21151 1 7 x 2 Bergstick J3 SAMTEC TSW 107 07 S D 1 2 Pin Terminal Block TB1 On Shore Technology ED500 2DS Switches 3 SPST Pushbutton S...

Страница 55: ...00MHz crystal oscillator 2 1 external oscillator frequency input 2 1 FSRAM 2 1 ISSI compatible peripheral 2 2 JTAG port interface 2 1 On board power regulation 2 2 Parallel JTAG Host Target Interface...

Страница 56: ...ce ix RS 232 interface 2 1 2 6 level converter 2 6 schematic diagram 2 6 RS 232 Serial Communications 2 6 S SCI Preface ix SPI Preface x 2 2 SRAM Preface x external data 2 1 external program 2 1 SSI P...

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Страница 60: ...uits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty repres...

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