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FII-PRX100 Hardware Reference Guide

Fraser Innovation Inc

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communication baud rate.

•

Built-in oscillator and power-on reset circuit, the peripheral circuit is simple.

•

Support 5V, 3.3V power supply voltage

Figure 17.1 Schematics of USB Keyboard and Mouse

Figure 17.2 USB Interface Physical Picture

Pin assignment

Signal Name

FPGA Pin

CH9350_RST

M17

CH9350_RXD

H21

CH9350_TXD

H22

Содержание FII-PRX100

Страница 1: ...V1 2 FRASER INNOVATION INC FII PRX100 Hardware Reference Guide ...

Страница 2: ... Reference Guide Fraser Innovation Inc 1 53 Version Control Version Date Description 1 0 07 11 2019 Initial Release 1 1 07 17 2019 Modification of HDMI and Segment Display Decoders 1 2 07 18 2019 Modification of JTAG Part ...

Страница 3: ...al Offenders will be held liable for their legal responsibility Thank you for purchasing the FPGA development board Please read the manual carefully before using the product and make sure that you know how to use the product correctly Improper operation may damage the development board This manual is constantly updated and it is recommended that you download the latest version when using Official ...

Страница 4: ...02 20 6 Gigabit Ethernet Interface 21 7 Push Button 24 8 AD DA Thermistor Photoresistor and Potentiometer 26 9 DIP Switch 28 10 LED 30 11 Configuration Chip FLASH 31 12 GPIO PMOD Expansion Interface 31 13 JTAG Interface 34 14 UART Interface 36 15 SRAM 38 16 Audio 42 17 USB Keyboard and Mouse Interface 43 18 TFT LCD Interface 46 19 40 pin Extended GPIO Interface 48 20 High Speed Bus Connector 49 3 ...

Страница 5: ...TIX 7 series It was initial released in 2018 This development board is resource rich and high speed making it an ideal platform for learning and engineering research This development board has been spent a lot on system design PCB design and function creation It could even be said comprehensive and powerful PRX100 Development Board Full View ...

Страница 6: ...re is to complete the power supply and download functions FPGA ARTIX 7 Gigabit Ethernet Interface 6 digits 7 segment decoders FLASH 128Mbit Back Potentiometer EEPROM AT24C02 Back 50M Oscillator Power Interface AD DA Back GPIO Interface External A D Interface 8 LEDs 8 Switches Reset Figure 1 PRX100 System Block Diagram Ethernet Chip RTL8211E USB1 USB2 USB3 USB4 7 Push Buttons External I2C Interface...

Страница 7: ...rough which it can simulate light control 1 thermistor which can collect temperature or analog temperature alarm function 1 potentiometer which can simulate voltage change 1 PCF8591 AD DA conversion chip reserved external interface free input and output Onboard 50MHz and 32 768kHz oscillators provide stable clock signals to the development board 8 bit switch 8 bit LED 1 128Mbit Flash chip 4 GPIO e...

Страница 8: ...er no external RISC V JTAG emulator required 1 UART asynchronous serial interface 2 SRAMs with a capacity of 16Mbit a pair of audio input and output interfaces 1 PCIE interface 4 USB interfaces 2 for the mouse and keyboard interface 2 for the universal serial interface 1 USB USB B to UART interface for serial communication 1 TFTLCD touch screen interface which can realize the display and operation...

Страница 9: ... As shown below Figure 1 2 External Power Supply Interface Figure 1 3 USB Power Supply and Download Interface Figure 1 4 Power Selection Jumper J23 2 Part of the FPGA BANK voltage is determined by selection jumpers J9 J10 Voltage of BANK34 and BANK35 in development board in order to adapt to a variety of external signals is adjustable power supply specifically by two common voltage options 1 8V an...

Страница 10: ... 1 5 BANK Voltage Selection 3 The program download selection is jumper J6 Use the external downloader to connect to the JTAG interface to download J6 1 2 connection is downloaded when using the JTAG interface As shown below Figure 1 6 Program Download Selection Jumper J6 ...

Страница 11: ...o the theme such as protection circuits or filter circuits will be eliminated Please pay attention to that For the source material please refer to the attached schematic 1 FPGA As mentioned above this development board FPGA model is XC7A100T 2FGG676I which is the latest generation of high performance FPGA of Xilinx Figure 2 1 FPGA Physical Picture Figure 2 2 Chip Resources 2 Power Supply Interface...

Страница 12: ...Power Supply Interface The second way is to use the USB cable to connect the CPU_TAG interface See Figure 2 4 Figure 2 4 Internal Power Supply Interface It should be noted that regardless of the power supply method the power selection jumper needs to be connected to the correct position As shown below Figure 2 5 Power Supply Selection Jumpers By the way to mention the power supply circuit of the d...

Страница 13: ...PC_USB5V power supply from the USB port is connected to the pin 3 of J23 With which of the two is connected to the 2nd pin it powers the development board There is no problem when the two power supplies are connected at the same time Figure 2 6 External Power Supply Schematics ...

Страница 14: ...r supply is connected to the VCC5V0 level network of the development board and then converted to the 1 0V FPGA core voltage 1 8V or 3 3V Among them 1 8V and 3 3V are the BANK voltage of the FPGA The two voltages are provided to meet the level standards of various external signals The conversion circuit is shown below Figure 2 8 Schematics of the 3 3V Power Supply ...

Страница 15: ... 9 Schematics of the 1 8V Power Supply Figure 2 10 Schematics 1 0V Power Supply If we look at the power supply of the FPGA we can see these kinds of voltages to highlight the topic the screenshot skips the irrelevant circuit Figure 2 11 Schematics of the FPGA Power Supply 1 ...

Страница 16: ...isted For more details please refer to the full version schematics 3 Segment Display Decoders Figure 3 1 Segment Decoders One type of segment display is a semiconductor light emitting device The segment display can be divided into a seven segment display decoder and an eight segment display decoder The difference is that the eight segment display decoder has one more unit for displaying the decima...

Страница 17: ... the anodes of the LEDs are connected Figure 3 3 Schematics of Common Anode Decoders To illuminate a segment of an 8 segment decoder the level of the corresponding pin needs to be pulled low when the pin is set high the corresponding field will not light This development board uses a 6 in one eight segment decoder The schematics is shown below ...

Страница 18: ...an be noticed The same segments of the six in one decoders are connected a total of eight pins and with six control signal pins a total of 14 pins as shown in Figure 3 4 Among them SEG_PA SEG_PB SEG_PC SEG_PD SEG_PE SEG_PF SEG_PG SEG_DP correspond to the A B C D E F G DP of decoder SEG_3V3_D 0 5 are six control pins of the decoders which are also active low When the control pin is low the correspo...

Страница 19: ...present the image display mode is also constantly developing The image display interface is also gradually transitioning from the old VGA interface to the new DVI or HDMI interface HDMI is the abbreviation of High Definition Multimedia Interface It is a digital video audio interface technology which is a dedicated digital interface for image transmission It can transmit audio and video signals at ...

Страница 20: ...nt Signal Name FPGA Pin HDMI INT E18 HDMI SCL R20 HDMI SDA R21 HDMI VSYNC A25 HDMI HSYNC C24 HDMI CLK B19 HDMI HPD H16 HDMI D35 F15 HDMI D34 E16 HDMI D33 D16 HDMI D32 G17 HDMI D31 E17 HDMI D30 F17 HDMI D29 C17 HDMI D28 A17 HDMI D23 B17 HDMI D22 C18 HDMI D21 A18 HDMI D20 D18 HDMI D19 D20 HDMI D18 A19 HDMI D17 B20 HDMI D16 A20 ...

Страница 21: ...19 5 EEPROM AT24C02 EEPROM is generally used in the instrumentation design It is often used as a storage for some parameters Data is not lost when power is off and it is easy to operate It is an ideal storage device The development board contains an EEPROM model AT24C02 with a capacity of 2kbit 256 8bit consisting of a 256 byte block that communicates over the IIC bus The onboard EEPROM is designe...

Страница 22: ...e FPGA Pin SDA R21 SCL R20 6 Gigabit Ethernet Interface Ethernet is currently the most commonly used data communication method Ethernet is getting faster and faster from the initial 10Mb s to the later 100Mb s and to 1000Mb s now The development board is equipped with an RTL8211E Gigabit Ethernet chip The RTL8211E is a highly integrated network receiving PHY chip from Realtek It is compliant with ...

Страница 23: ...lude Meets 1000Base T IEEE802 3ab standard Compliant with 100Base TX IEEE802 3u standard Compliant with 10Base T IEEE802 3 standard Support IEEE 802 3 RGMII interface Support IEEE 802 3 GMII MII interface only RTL8211EG support Support for Wake on LAN Support for interrupt function Support crossover detection and auto correction Support half duplex full duplex operation 1000 MHz communication CAT ...

Страница 24: ...Innovation Inc 23 53 Figure 6 1 Schematics of Gigabit Ethernet Chip Figure 6 2 Gigabit Ethernet Physical Picture Gigabit ethernet pin assignment Signal Name FPGA Pin RG0_RXCTL M14 RG0_RXD0 L14 RG0_RXD1 K15 RG0_RXD2 J14 RG0_RXD3 J15 RG0_RXCK K21 ...

Страница 25: ...D0 K16 RG0_TXD1 K17 RG0_TXD2 K18 RG0_TXD3 H19 RG0_TXCTL G20 NPHY_MDC F22 NPNY_MDIO J20 7 Push Button The development board has 8 push buttons 7 of which are programmable buttons and 1 is for system reset The default is set high and can be pressed low Schematics is shown in Figure 7 1 ...

Страница 26: ...FII PRX100 Hardware Reference Guide Fraser Innovation Inc 25 53 Figure 7 1 Schematics of Push Buttons Figure 7 2 Push Button Physical Picture ...

Страница 27: ... I2C bus interface The three address pins A0 A1 and A2 of PCF8591 can be used for hardware address programming the three addresses on the development board are connected to GND that is the device address is 7 B1001000 allowing access on the same I2C bus PCF8591 devices without additional hardware The address control and data signals input and output on the PCF8591 device are serially transmitted o...

Страница 28: ... Auto incremented channel selection Analog voltage ranges from VSS to VDD On chip track and hold circuit 8 bit successive approximation A D conversion Multiplying DAC with one analog output The schematics is shown in Figure 8 1 to make the theme clearer the figure has been modified for the design drawings Figure 8 1 Schematics of AD DA Figure 8 2 PCF8591 Physical Picture ...

Страница 29: ...otentiometer connect J22 with a jumper cap When using the thermistor connect J24 When using a photoresistor connect J21 PCF8591 pin assignment Signal Name FPGA Pin ADDA_I2C_SAD C19 ADDA_I2C_SCL E20 9 DIP Switch The 8 bit DIP switch is onboard and the FPGA pin gets high when the switch is turned on The schematics is shown as follows ...

Страница 30: ...erence Guide Fraser Innovation Inc 29 53 Figure 9 1 Schematics of DIP Switches Figure 9 2 DIP Switches Physical Picture DIP switches pin assignment Signal Name FPGA Pin SW0 N8 SW1 M5 SW2 P4 SW3 N4 SW4 U6 SW5 U5 SW6 R8 SW7 P8 ...

Страница 31: ...LEDs When the pin is low the LED emits light and when it is high the LED does not emit light The schematic is shown in Figure 10 1 Figure 10 1 Schematics of LED Figure 10 2 LED Physical Picture LED pin assignment Signal Name FPGA Pin LED0 N17 LED1 M19 LED2 P16 LED3 N16 LED4 N19 LED5 P19 LED6 N24 LED7 N23 ...

Страница 32: ...ograms in the FPGA Figure 11 1 shows the N25Q128A in the schematics Figure 11 1 Schematics of FLASH Figure 11 2 FLASH Physical Picture 12 GPIO PMOD Expansion Interface The development board has four GPIO interfaces and is also a standard PMOD interface The P1 and P2 interfaces each contain 6 standard IO pins of PFGA resources 2 GND signals and 2 adjustable power signals The P3 and P4 interfaces ...

Страница 33: ...s and 2 adjustable power signals It can be used with the BD5640 PMOD camera daughter board or the BD9226 high speed AD daughter board The daughter boards are available at the official online store The schematics is as follows Figure 12 1 Schematics of GPIO Figure 12 2 GPIO Physical Picture Figure 12 3 GPIO Interface with BD5640 Camera Daughter Board ...

Страница 34: ...P1 2 V22 Standard IO P1 3 V23 Standard IO P1 4 U24 Standard IO P1 5 GND P1 6 VCC jumper J18 P1 7 AA22 Standard IO P1 8 AA23 Standard IO P1 9 W23 Standard IO P1 10 V24 Standard IO P1 11 GND P1 12 VCC jumper J18 P2 1 U19 Standard IO P2 2 U14 Standard IO P2 3 U16 Standard IO P2 4 V16 Standard IO P2 5 GND P2 6 VCC jumper J18 P2 7 T15 Standard IO P2 8 U15 Standard IO P2 9 V17 Standard IO P2 10 V14 Stan...

Страница 35: ... P P3 8 K8 LVDS3 N P3 9 G5 LVDS4 P P3 10 F5 LVDS4 N P3 11 GND P3 12 VCC jumper J19 P4 1 H8 LVDS5 P P4 2 G8 LVDS5 N P4 3 E6 LVDS6 P P4 4 D6 LVDS6 N P4 5 GND P4 6 VCC jumper J19 P4 7 H7 LVDS7 P P4 8 G7 LVDS7 N P4 9 F8 LVDS8 P P4 10 F7 LVDS8 N P4 11 GND P4 12 VCC jumper J19 13 JTAG Interface Connect jumper J6 1 2 to use J4 or J5 as external download interface The JTAG schematics is shown in Figure 13...

Страница 36: ...erface Physical Picture JTAG pin assignment Signal Name FPGA Pin TCK H12 TCK GND TDO J10 TDO VCC TMS H11 TMS TDI H10 TDI The second JTAG interface is CPU_TAG which downloads the program for the RISC V CPU The physical picture and pin assignments are as follows Figure 13 3 RISC V Download Interface Physical Picture J4 J5 ...

Страница 37: ...with a USB 2 0 full speed function controller USB transceiver oscillator EEPROM and asynchronous serial data bus UART to support modem full featured signals without the need for any external USB devices Its characteristics are as follows Integrated USB transceiver no external resistors required Integrated clock no external oscillator required On chip power on reset circuit On chip voltage regulato...

Страница 38: ...rted data formats are data bit 8 stop bit 1 2 and check digit Intrinsic more than 512 byte receive buffer and 512 byte transmit buffer Hardware or X On X Off handshaking supported Figure 14 1 UART Schematics Figure 14 2 USB B Interface and CP2102 Chip Physical Picture UART pin assignment Signal Name FPGA Pin ...

Страница 39: ...namic random access memory DRAM needs to be updated periodically However when the power supply is stopped the data stored in the SRAM will disappear called volatile memory which is different from the ROM or flash memory that can store data after the power is turned off The development board has two Super SRAMs which are connected in parallel to a 32 bit data interface The maximum access space is u...

Страница 40: ...FII PRX100 Hardware Reference Guide Fraser Innovation Inc 39 53 Figure 15 1 Schematics of SRAM0 Figure 15 2 Schematics of SRAM1 ...

Страница 41: ...Pin SRAM0_CE_N F25 SRAM0_OE_N H23 SRAM0_WE_N L19 SRAM0_UB_N H24 SRAM0_LB_N G26 SRAM0_IO0 U21 SRAM0_IO1 U25 SRAM0_IO2 W26 SRAM0_IO3 Y26 SRAM0_IO4 AA25 SRAM0_IO5 AB26 SRAM0_IO6 AA24 SRAM0_IO7 AB24 SRAM0_IO8 AC24 SRAM0_IO9 AC26 SRAM0_IO10 AB25 SRAM0_IO11 Y23 SRAM0_IO12 Y25 SRAM0_IO13 W25 SRAM0_IO14 V26 SRAM0_IO15 U26 SRAM0_A0 SRAM1_A0 E26 ...

Страница 42: ...1_A8 L15 SRAM0_A9 SRAM1_A9 K23 SRAM0_A10 SRAM1_A10 J25 SRAM0_A11 SRAM1_A11 K22 SRAM0_A12 SRAM1_A12 H26 SRAM0_A13 SRAM1_A13 J26 SRAM0_A14 SRAM1_A14 J24 SRAM0_A15 SRAM1_A15 G25 SRAM0_A16 SRAM1_A16 G24 SRAM0_A17 SRAM1_A17 J21 SRAM0_A18 SRAM1_A18 J23 CE_N_SRAM1 E23 OE_N_SRAM1 F23 WE_N_SRAM1 J18 UB_N_SRAM1 F24 LB_N_SRAM1 K20 SRAM1_IO0 T14 SRAM1_IO1 T17 SRAM1_IO2 W18 SRAM1_IO3 U17 SRAM1_IO4 V18 SRAM1_IO...

Страница 43: ...tereo differential microphone preamplifiers with speakers headphones and differential stereo line output drivers to reduce the external components necessary for the application such as advanced on chip digital signal processing function with separate microphone or headphone amplifiers including a 5 band equaliser a mixed signal Automatic Level Control for the microphone or line input through the A...

Страница 44: ... Inc 43 53 Figure 16 1 Schematics of Audio Figure 16 2 Audio Interface and Chip Physical Picture Pin assignment Signal Name FPGA Pin WM_LRC H15 WM_BCLK F18 WM_ADCDAT G19 WM_DACDAT F20 WM_MCLK H17 WM_SCLK R20 WM_SDIN R21 17 USB Keyboard and Mouse Interface ...

Страница 45: ...otocol and does not require additional driver installation It supports Windows Linux MAG and other operating systems with built in HD device drivers The same chip can be configured as the host computer mode and the client computer mode respectively connected to USB Host and USB keyboard and mouse in the same mode to configure different working states suitable for a variety of applications Support ...

Страница 46: ...Built in oscillator and power on reset circuit the peripheral circuit is simple Support 5V 3 3V power supply voltage Figure 17 1 Schematics of USB Keyboard and Mouse Figure 17 2 USB Interface Physical Picture Pin assignment Signal Name FPGA Pin CH9350_RST M17 CH9350_RXD H21 CH9350_TXD H22 ...

Страница 47: ...l is connected Adaptable to 3 5 inches touch LCD module TFT LCD screen 320X480 Interface and matching LCD screen LCD screen available in official online store as shown below Figure 18 1 LCD Interface Physical Picture Figure 18 2 3 5 LCD Touch Display Pin assignment Signal Name FPGA Pin Description Pin 1 H14 CS Pin 2 B26 RS Pin 3 D24 WR Pin 4 C26 RD Pin 5 E21 RST ...

Страница 48: ...DB6 Pin 13 AB24 DB7 Pin 14 AC24 DB8 Pin 15 AC26 DB9 Pin 16 AB25 DB10 Pin 17 Y23 DB11 Pin 18 Y25 DB12 Pin 19 W25 DB13 Pin 20 V26 DB14 Pin 21 U26 DB15 Pin 22 GND Pin 23 T14 BL Pin 24 VCC3V3 Pin 25 VDD3V3 Pin 26 GND Pin 27 GND Pin 28 BL_VDD Pin 29 T17 MISO Pin 30 W18 T_MOSI Pin 31 U17 T_PEN Pin 32 V18 T_BUSY Pin 33 G15 T_CS Pin 34 W19 T_CLK Pin 35 G_PAD Pin 36 G_PAD ...

Страница 49: ...nal Name FPGA Pin Description Pin 1 H9 GPIO_0 Pin 2 J8 GPIO_1 Pin 3 A5 GPIO_2 Pin 4 G9 GPIO_3 Pin 5 B5 GPIO_4 Pin 6 A4 GPIO_5 Pin 7 A3 GPIO_6 Pin 8 B4 GPIO_7 Pin 9 B2 GPIO_8 Pin 10 A2 GPIO_9 Pin 11 F4 GPIO_10 Pin 12 D5 GPIO_11 Pin 13 G6 GPIO_12 Pin 14 C4 GPIO_13 Pin 15 H4 GPIO_14 Pin 16 D4 GPIO_15 Pin 17 J4 GPIO_16 Pin 18 E3 GPIO_17 Pin 19 E5 GPIO_18 Pin 20 C2 GPIO_19 ...

Страница 50: ...0 Pin 32 G2 GPIO_31 Pin 33 G1 GPIO_32 Pin 34 H3 GPIO_33 Pin 35 K7 IO22_P Pin 36 K6 IO22_N Pin 37 GND Pin 38 GND Pin 39 VCC3V3 Pin 40 VCC3V3 20 High Speed Bus Connector PCI Express Peripheral Component Interconnect Express connector is used here It is not related to the PCIE bus standard The main advantage is the high data transfer rate The onboard PCIE connector can be used with the BD5640 camera ...

Страница 51: ... Figure 20 2 BD5640 Daughter Board Pin assignment Signal Name FPGA Pin Description A1 A2 12V A3 12V A4 GND A5 H2 JTAG2 TCK A6 H1 JTAG3 TDI A7 J3 JTAG4 TDO A8 K3 JTAG5 TMS A9 3 3V A10 3 3V A11 PERST A12 GND A13 N3 REFCLK A14 N2 REFCLK A15 GND A16 M2 PERp0 A17 L2 PERn0 A18 GND A19 RESERVED A20 GND A21 N7 PERp2 ...

Страница 52: ...0 T3 PERn3 A31 GND A32 R6 RESERVED B1 12V B2 12V B3 12V B4 GND B5 R3 SMCLK B6 P3 SMDAT B7 GND B8 3 3V B9 K2 JTAG1 TRST B10 3 3Vaux B11 WAKE B12 L3 RESERVED B13 GND B14 K1 PETp0 B15 J1 PETn0 B16 GND B17 PRSNT 2 B18 GND B19 N1 PETp1 B20 M1 PETn1 B21 GND B22 GND B23 M7 PETp2 B24 L7 PETn2 B25 GND B26 GND B27 U2 PETp3 B28 U1 PETn3 B29 GND B30 P5 RESERVED ...

Страница 53: ...FII PRX100 Hardware Reference Guide Fraser Innovation Inc 52 53 B31 P6 PRSNT 2 B32 GND ...

Страница 54: ... https www nxp com docs en data sheet PCF8591 pdf 2 https www verical com datasheet realtek semiconductor phy rtl8211e vb cg 2635459 pdf page 36 zoom 100 0 105 3 https www silabs com documents public data sheets CP2102 9 pdf 4 https www mouser com ds 2 76 WM8978_v4 5 1141768 pdf ...

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