Forlinx FET6254-C, Руководство по оборудованию

Страница: 32 / 73

Hardware manual
OK6254-C FET6254-C
www.forlinx.net
- 32 -
TRC_CTL O Trace control P3_76
TRC_DATA0 O Trace data 0 P3_74
TRC_DATA1 O Trace data 1 P3_72
TRC_DATA2
O
Trace data 2 P3_70
TRC_DATA3
O
Trace data 3 P3_68
TRC_DATA4 O Trace data 4 P3_66
TRC_DATA5
O
Trace data 5 P3_64
TRC_DATA6 O Trace data 6 P4_77
TRC_DATA7 O Trace data 7 P4_67
TRC_DATA8 O Trace data 8 P4_65
TRC_DATA9
O
Trace data 9 P4_63
TRC_DATA10 O Trace data 10 P4_69
TRC_DATA11 O Trace data 11 P4_73
TRC_DATA12
O
Trace data 12 P4_45
TRC_DATA13
O
Trace data 13 P4_61
TRC_DATA14 O Trace data 14 P4_71
TRC_DATA15 O Trace data 15 P4_51
TRC_DATA16
O
Trace data 16 P4_53
TRC_DATA17
O
Trace data 17 P4_55
TRC_DATA18 O Trace data 18 P4_57
TRC_DATA19 O Trace data 19 P3_46
TRC_DATA20
O
Trace data 20 P3_48
TRC_DATA21
O
Trace data 21 P3_50
TRC_DATA22 O Trace data 22 P3_52
TRC_DATA23 O Trace data 23 P3_54
MCU Domain
Peripheral Signal I/O Default function Pin No.
JTAG
EMU0 IO Emulation control 0 P2_43
EMU1 IO Emulation control 1 P2_45
TCK I JTAG test clock input P2_53
TDI I JTAG test data input P2_57
TDO OZ JTAG test data output P2_59
TMS I JTAG test mode selection input P2_55
TRSTn I JTAG reset P2_51
2.6.11 EPWM
MAIN Domain
Peripheral Signal I/O Default function Pin No.
EPWM
EHRPWM_SOCA O EHRPWM start to convert A P2_50
EHRPWM_SOCB
O
EHRPWM start to convert B P2_52
EHRPWM_TZn_IN0 I EHRPWM trigger zone input 0(lower power valid) P2_40
EHRPWM_TZn_IN3 I EHRPWM trigger zone input 3(lower power valid) P2_44
EHRPWM_TZn_IN4 I EHRPWM trigger zone input 4(lower power valid) P2_46
EHRPWM_TZn_IN5 I EHRPWM trigger zone input 5(lower power valid) P2_32
EPWM0
EHRPWM0_A IO EHRPWM output A P2_34
P2_74
EHRPWM0_B IO EHRPWM output B P2_72,
P2_32,
EHRPWM0_SYNCI I Synchronously input from external pin to EHRPWM P2_54