Force SYS68K/CPU-30 R4, Техническое справочное руководство

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Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual
Page 38
Write cycles are handled differently. In the case of a long-word access
aligned to a 4-byte boundary, the DRAM can be written immediately.
The parity info generated by FGA-002 will be written additionally to the
DRAM. A synchronous termination signal (STERM) is asserted, and the
cycle completed.
For all other write cycles (byte, word, long-word unaligned), the
momentary valid parity info stored in DRAM must be read. Then the
write to RAM Memory will be performed. Therefore, only the necessary
data will be written, the remaining data already stored in DRAM will stay
unmodified. Additionally, the new parity info generated by FGA-002 will
be merged with the read parity info from DRAM and finally all four
parity bits are written to DRAM. The synchronous termination signal
(STERM) will be generated to complete the cycle.
All write cycles are terminated before they are fully processed to allow
the master writing to DRAM to continue its operations (write posting).
3.4.2.1 Bank Selection
of DRAM
The bank selection depends on memory size. The Dual-Banks
architecture implements an interleaved organized DRAM (four
consecutive bytes located in bank A, the next four consecutive bytes
located in bank B, ...). The Single-Bank architecture implements a non-
interleaved organized DRAM.
Shared RAM byte parity generation and check work for both local and
VMEbus accesses. If a parity error is detected during a VMEbus slave
read access, the CPU board drives BERR, informing the VMEbus master
about the parity error. On all local accesses, a normal STERM will be
generated, plus an interrupt on a software programmable level. The
access address is stored inside the FGA-002 Gate Array allowing easy
software controlled detection of the cycle which caused the parity error.
The Shared RAM is accessed from the VMEbus via FGA-002. The start
and end access addresses are programmable in 4 Kbyte steps. The
1. FPM: Fast Page Mode
Table 13: Used Device Types for the Shared Memory
DRAM Device Device Capacity Total Capacity Bank Supported Product
1M * 4 FPM
1)
9 * 1 Mbit * 4 4 Mbyte 1 CPU-30ZBE R4
1M * 4 FPM 18 * 1 Mbit * 4 8 Mbyte 2 CPU-30BE/8 R4
4M * 4 FPM 9 * 4 Mbit * 4 16 Mbyte 1 CPU-30BE/16 R4
4M * 4 FPM 18 * 4 Mbit * 4 32 Mbyte 2 factory option
1M * 4 FPM 9 * 1 Mbit * 4 4 Mbyte 1 CPU-30Lite/4 R4
1M * 4 FPM 18 * 1 Mbit * 4 8 Mbyte 2 CPU-30Lite/8 R4