Force SYS68K/CPU-30 R4, Техническое справочное руководство

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Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual
Page 96
3.17 VMEbus Master Interface
3.17.1 Data Transfer
Size of the
VMEbus
Interface
The memory map of the CPU board divides the 4-Gbyte address space of
the 68030 microprocessor into areas of local memory, local I/O,
FGA-002 internal registers, and VMEbus space. The VMEbus space is
by far the largest portion of the address map. It is divided into ranges
where different address bus widths (A32/A24/A16) and different data bus
widths (D32/D16) will be used. The VMEbus interface also contains
address ranges where the data transfer size is software programmable to
be 16 or 32 bits wide.
In address ranges where the data transfer bus width is limited to 16 bits
and a 32-bit transfer is attempted, the hardware on the CPU board will
perform two consecutive transfers automatically, so that no overhead in
software is necessary.
The following table lists the VMEbus address ranges and their associated
address and data bus sizes in detail.
SEE ALSO: For further information, please refer to Section 3.4.5,
‘Shared RAM Addressing,’ on page 40.
VMEPROM includes a command (MEM) to set up the data bus transfer
size of the three programmable areas. For example:
MEM displays the current data bus transfer size.
MEM 16 sets 8/16-bit data transfer size.
MEM 32 sets 8/16/32-bit data transfer size.
In addition, VMEPROM uses one bit of the rotary switches available on
the front panel to select the data bus size of the VMEbus after RESET or
power up.
1. VMEbus start address is dependent on the amount of on-board shared DRAM.
Table 30: Data Bus Size of the VMEbus (Master Interface)
Start Address End Address Address Size Data Size
xxxx.0000
16
1)
FAFF.FFFF
16
A32 Prog.
FB00.0000
16
FBFE.FFFF
16
A24 Prog.
FBFF.0000
16
FBFF.FFFF
16
A16 Prog.
FC00.0000
16
FCFE.FFFF
16
A24 16
FCFF.0000
16
FCFF.FFFF
16
A16 16
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