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SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description
Page 89
The figure below shows a simplified functional block diagram of the
Ethernet Interface.
Figure 5: Functional Block Diagram of the Ethernet Interface
3.13.2 The Am7990
LANCE
The LANCE is a 68-pin VLSI device that provides many functions for
the connection of a microprocessor to an Ethernet network.
In the transmitting mode the LANCE transfers data from the buffer
SRAM to an internal FIFO (called a SILO). The serial output of the SILO
is connected to the Am7992 SIA, where the data is sent to the Ethernet
cable.
In the receiving mode the SIA transfers the received data from the
Ethernet cable to the serial SILO input. The LANCE then transfers the
data from the SILO to the buffer SRAM in 8-word (16 byte) bursts.
SEE ALSO: For detailed information please refer to the AM7990
LANCE data sheet in Section 4, ‘Circuit Schematics and Data Sheets,’ on
page 115.
3.13.2.1 Address Map
of the LANCE
Registers
The LANCE contains one Register Address Pointer (RAP) and four
Control/Status Registers (CSR[0..3]). To read or write to CSR1, CSR2,
or CSR3, the LANCE must be stopped by setting the stop bit in CSR0.
Therefore, CSR0 and RAP can be accessed at any time that the LANCE
is in the slave mode. To read or write to CSR1 through CSR3, the number
of the CSR must be written to the RAP first. The address map is shown in
the following table.
Table 29: LANCE Register Layout
Default
I/O Base Address:
Offset:
$FEF8 0000
$0000 0000
Address
(HEX)
Offset
(HEX)
Reset
Value
Label Description
FEF80002
FEF80000
FEF80000
FEF80000
FEF80000 2
0
0
0
0 0000
0004
N/A
N/A
N/A
RAP
CSR0
CSR1
CSR2
CSR3
Register Address Pointer
Control and Status Register 0
Control and Status Register 1
Control and Status Register 2
Control and Status Register 3
N/A = NOT APPLICABLE OR NOT EFFECTED
CPU Am7990 SRAM Am79928 AUI
SIA LANCE
TRANSFORMER
LOCAL BUS LANCE BUS
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