
9000A-006 Service
2-10
Clock counter (U20A, U8 U9, U10) creates a STOP edge after a certain number of gated
CLOCK pulses. This feature allows selection of agate time that is equivalent to a specified
number of gated clock pulses. The clock counter receives the gated CLOCK pulses fed to
the CRC and events sections and decrements from a preset (at the time of initialization)
count. When the counter reaches zero, it generates a zero-count output to set the stop flip-
flop (U48B) and immediately inhibit the generation of gated CLOCK pulses.
CRC Section
2-7.
The CRC section receives the gated CLOCK pulses from the gate section and the delayed
data (high and low) from the delay section and generates the hexadecimal signature of the
data through a cyclic redundancy check. As shown in Figure 2-4, the delayed data from
the probe is applied through a feedback gating circuit to a 16-bit shift register. The shift
register consists of four 4-bit registers, U63 through U66. Each register has serial and 4-bit
parallel inputs and outputs, where the output of the first is connected to the input of the
second, etc. This arrangement allows data to be shifted through the registers in either
serial or four-bit parallel fashion. The four-bit parallel output of the fourth register is fed to
the transmit buffer, U3, located in the control section.
Since the CRC register has both parallel and serial inputs/ outputs, it can be operated in
both parallel and serial modes. When a read probe operation is in progress, the gated
CLOCK signal operates the register in the serial mode. In the serial mode, high and low
data is applied to the serial input of the first of the four registers and carries through to the
fourth as gated CLOCK signals occur. To provide the CRC action of the register, four
outputs are taken from the registers. These outputs are fed through exclusive-or gates and
clocked through pipeline registers back to the feedback gating circuit formed by U21,
U25, and U20.
The feedback gating is necessary to achieve the standard CRC signature result from the
probe data and gated CLOCK pulses. The pipeline registers permit the CRC section to
operate at a higher speed than that possible with the exclusive-or gates alone.
To handle invalid probe data levels (both VALID-HI and VALID-LOW signals at a low
level), a last level register (2D input of U22) is used to store the last valid data level and
apply it to the feedback gating. This feature prevents the CRC register from attempting to
generate a signature using invalid data. Each register in the CRC section is cleared by the
CLR-CRC signal from the control section.
The CRC register also operates in the parallel mode. This mode is used at the end of the
signature computation to shift the accumulated signature, four bits (nibble) at a time, onto
the pod bus via the transmit buffer. Four shift (load) operations are used to place the four
nibbles of signature data on the pod bus. As each shift operation takes place, the parallel
output of the events section (EVT-20 through EVT-23) is shifted into and through the CRC
register. The CRC register provides the path for the event count and waveform data to
reach the transmit buffer and pod bus.
The four-bit output of the last CRC register is fed to the input of the transmit buffer (U3)
located in the control section. When the Troubleshooter issues a read-next op code (80H)
to the control section, the main decoder enables the transmit buffer. Since the transmit
buffer contains the output of the last CRC register, the output of the last CRC register is
placed on the pod bus to the Troubleshooter.
Содержание 9000A-006
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