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FIBOCOM_NL952-NA_Hardware_User_Manual
Page 16 of 57
Pin Pin Name
I/O
Reset Value
Pin Description
Level
52 CLKREQ#
I/O
PD
Asserted by device to request a PCIe
reference clock be available (active clock
state) in order to transmit data. It also
used by L1 PM Sub states mechanism,
asserted by either host or device to
initiate an L1 exit.
Active low, open drain output and should
add external pull up on platform
3.3/1.8V
53 REFCLKN
I
PCIe Reference Clock signal
Negative
54 PEWAKE#
O
PD
Asserted to wake up system and
reactivate PCIe link from L2 to L0, it
depends on system
whether supports wake up functionality.
Active low, open drain output and should
add external pull up on platform
3.3/1.8V
55 REFCLKP
I
PCIe Reference Clock signal
Positive
56 RFFE_SCLK
O
PD
MIPI Interface Tunable ANT,
RFFE clock
1.8V
57 GND
GND
Power Supply
58 RFFE_SDATA
I/O
PD
MIPI Interface Tunable ANT,
RFFE data
1.8V
59 ANTCTL0
O
PD
Tunable ANT CTRL0
1.8V
60 COEX3
I/O
TBD
Wireless Coexistence between WWAN
and WiFi/BT modules, based on BT-SIG
coexistence protocol. COEX_EXT_FTA,
Reserved
1.8V
61 ANTCTL1
O
PD
Tunable ANT CTRL1
1.8V
62 COEX_RXD
I
PD
Wireless Coexistence between WWAN
and WiFi/BT modules, based on BT-SIG
coexistence protocol. UART receive
signal(WWAN module side), Reserved
1.8V
63 ANTCTL2
O
PD
Tunable ANT CTRL2
1.8V
64 COEX_TXD
O
PD
Wireless Coexistence between WWAN
and WiFi/BT modules, based on BT-SIG
coexistence protocol. UART transmit
signal(WWAN module side), Reserved
1.8V
65 ANTCTL3
O
PD
Tunable ANT CTRL3
1.8V
66 SIM1_DETECT
I
PD
SIM1 Detect, internal pull up(390K
Ω
),
active high
1.8V
67 RESET#
I
PU
WWAN reset input, active low, internal
pull up(40K
Ω
)
1.8V