Functional Description
CPC805
C P C 8 0 5 U s e r M a n u a l
37
© 2 0 1 2 F a s t w e l v . 0 0 1 a E P r e
2.3
SPI Controller
2.3.1
SPI Controller Registers
Table 2-13:
SPI Controller and User LEDs Registers
Index
I/O Port Address
Type
Hard Reset
Configuration Register
310h
R/W
00h
FRAM address value [7:0]
311h
R/W
00h
FRAM address value [14:8]
312h
R/W
00h
SPI data value [7:0]
313h
R/W
00h
SPI Control/Status register
[7] – Busy status
[6] – Last 1K fram lock status
[5] – FPGA EEPROM mode
[4] – Reserved
[3] – Mode [0-fram, 1-ext dev)
[2] – CPOL
[1] – CPHA
[0] – BURST mode
314h
R/W
00h
SPI control reg 2
[7:5] – Reserved
[4:2] – FREQ select
000 – 25 MHz
001 – 12.5 MHz
010 – 6.25 MHz
011 – 3.125 MHz
100 - 1.5625 MHz
[1:0] – ext dev select (if MODE=1)
00 – CS0
01 – CS1
10 – CS2
11 – Reserved
HL2 User LEDs Control Register
317h
R/W
00h
User LEDs control
[7:2] – Reserved
[1] – Led2 (red) On/Off
[0] – Led1 (green) On/off
SPI controller supports two operation modes – FRAM or EXTDEV, it is selected in Control Register
(313h bit <3>). In FRAM mode the controller automatically forms sequence for accessing FRAM
memory on SPI bus; address from registers 310h and 311h in read/write modes, 312h – Data
register. In this mode external devices (CS0-CS2) are not active and FRAM memory is always
selected on CPC805.
