User Manual
DIC324
by the code T[7:0]). Value of the least significant bit corresponds to the
filling frequency period (in accordance with code G[7:0] - from 80 ns to
10.24 µs).
3.3.2 Configuration FPGA D11 - Digital_Outputs
Basic option of controlling the outputs enables to implement the following
capabilities:
8 digital output channels;
Single-wire or two-wire signal connection;
Switching
output
voltages/currents:
60
V / 500 mA (where
the differential type of load connection is used);
automatic reset through power supply activation and
hardware RESET;
Control of outputs states (up to optical isolation).
3.3.2.1
Integrated parts of the diagram
The block diagram of digital output includes:
output register (RG)
output buffer (BUF)
optical isolation unit (Opt)
output switches (OUT)
Fig. 3-4: Integrated parts of the block-diagram
3.3.2.2
Designation of outputs ports
Control of DIC324 is carried out via the I/O ports. Addresses of the ports are set with
regard to the Base Address (BA), set by the SA1 switch.
Register of outputs
is available through recording and reading via the port with BA+0
address.
Switching the output
x
of the board is carried out by setting the relevant bit in the register of
outputs. Reading the buffer if outputs makes it possible to determine the current state of outputs (1
- closed, 0 - open).
Basic option of controlling the outputs enables to implement the following capabilities:
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