FabiaTech Low Power FB2652, Руководство пользователя

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Chipset Features Setup
This section describes the configuration of the board’s chipset features.
DRAM Timing Selectable
SPD represents Serial Presence Detect. It is an 8-bit, 2048 bits EEPROM, built on the
SDRAM for different frequencies. If the installed SDRAM supports SPD function,
select SPD. If not, you can select based on other access time of the SDRAM.
Available Options: By SPD, Manual
Default setting: By SPD
CAS Latency Time
This field specifies the latency for the Synchronous DRAM system memory signals.
Available Options: 2.5, 2
Default setting: 2.5
Active to Precharge Delay
This field specifies control the number of DRAM for an access cycles.
Available Options: 7,6,5
Default setting: 7