FabIATech Corporation
Bit 5: Data Set Ready (DSR)
Bit 6: Ring Indicator (RI)
Bit 7: Received Line Signal Detect (RSLD)
Divisor Latch (LS, MS)
LS
MS
Bit 0:
Bit 0
Bit 8
Bit 1:
Bit 1
Bit 9
Bit 2:
Bit 2
Bit 10
Bit 3:
Bit 3
Bit 11
Bit 4:
Bit 4
Bit 12
Bit 5:
Bit 5
Bit 13
Bit 6:
Bit 6
Bit 14
Bit 7:
Bit 7
Bit 15
Desired Baud
Rate
Divisor Used to Generate 16x
Clock
300 384
600 192
1200 96
1800 64
2400 48
3600 32
4800 24
9600 12
14400 8
19200 6
28800 4
38400 3
57600 2
115200 1
65
Содержание FB2642
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Страница 48: ...FabIATech Corporation 42 ...
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Страница 75: ...FabIATech Corporation Appendix Dimension 184 9 4 1 18 4 6 4 6 121 9 13 8 5 1 4 6 8 8 23 4 24 5 24 6 Unit mm 69 ...
