FabiaTech FB2402, Руководство пользователя

Страница: 61 / 77

FabiaTech Corporation
55
NOTE: If you program the watchdog to generate IRQ15 signal when it times out,
you should initial IRQ15 interrupt vector and enable the second interrupt
controller (8259 PIC) in order to enable CPU to process this interrupt. An
interrupt service routine is required too. Before you configure the IRQ
signals, make sure they are not conflicted with other devices, like Floppy,
printer, serial ports, LAN, and PS/2 mouse, etc. Refer to Table 2-2 Interrupt
Controller for IRQ reference.
¾
Timeout Status – WDT0 and WDT1
WDT 0 3Ch
WDT 1 ADh
Bit 7 0 Timer timeout not happened - Read only.
1 Timer timeout happened - Read only.
Bit 6 Write this bit “1” to reset watchdog timer ( Only for WDT 0 .)
Bit 5-0 Other function.
Please do not modify these bits.
¾
Reload Register - WDT1
WDT 1 AEh
Bit 7-0 Writer this port to reload Watchdog Timer Counter.
The read date is unknown.
Setup Watchdog Timer Step - WDT0 and WDT1
¾
WDT0 setup Step:
1. Unlock Registers by Index 22h and data port 23h.
2. Index 37h Set Bit 6 = 0 to disable the watchdog timer 0 (WDT0).
3. Write the desired counter value to index 3Bh, 3Ah, and 39h.
4. Index 37h Set Bit 6 = 1 to enable the timer, the counter will begin to count up.
5. When counter reaches the setting value, the time out will generate signal setting
by index 38h bit [7:4].
6. BIOS can read index 3Ch Bit 7 to decide whether the Watchdog timeout event
will happen or not.
To clear the watchdog timer counter:
1. Index 3Ch set Bit 6 = 0 to disable timer. This will also clear counter at the same
time.