Exar XRT73L04, Руководство пользователя

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XRT73L04A
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.3
II
1.0 SELECTING THE DATA RATE ............................................................................................................... 25
1.1 C
ONFIGURING
C
HANNEL
(
N
) ............................................................................................................ 25
Table 2:Hexadecimal Addresses and Bit Formats of XRT73L04A Command Registers ............................... 26
Table 3:Selecting the Data Rate for Channel(n) via the E3_(n) and STS-1/DS3_(n) input pins (Hardware Mode)
27
C
OMMAND
R
EGISTER
, CR4-(
N
) ........................................................................................................... 27
Table 4:Selecting the Data Rate for Channel(n) via the STS-1/DS3_(n) and the E3_(n) bit-fields within the Ap-
propriate Command Register (HOST Mode) ..................................................................................... 27
2.0 THE TRANSMIT SECTION ...................................................................................................................... 28
2.1 T
HE
T
RANSMIT
L
OGIC
B
LOCK
......................................................................................................... 28
Accepting Dual-Rail Data from the Terminal Equipment ................................................................... 28
Figure 14. The typical interface for the Transmission of Data in a Dual-Rail Format from the Transmitting Ter-
minal Equipment to the Transmit Section of a channel .................................................................... 28
Figure 15.The XRT73L04A Samples the data on the TPData and TNData input pins ................................... 29
Accepting Single-Rail Data from the Terminal Equipment ................................................................ 29
C
OMMAND
R
EGISTER
CR3-(
N
) ............................................................................................................ 29
Figure 16.The Behavior of the TPData and TxClk Input Sgnals, while the Transmit Logic Block is Accepting Sin-
gle-Rail Data from the Terminal Equipment ..................................................................................... 29
2.2 T
HE
T
RANSMIT
C
LOCK
D
UTY
C
YCLE
A
DJUST
C
IRCUITRY
................................................................. 29
2.3 T
HE
HDB3/B3ZS E
NCODER
B
LOCK
............................................................................................... 30
B3ZS Encoding .................................................................................................................................. 30
Figure 17.An Example of B3ZS Encoding ...................................................................................................... 30
HDB3 Encoding ................................................................................................................................. 30
Figure 18.An Example of HDB3 Encoding ..................................................................................................... 31
Disabling the HDB3/B3ZS Encoder ................................................................................................... 31
C
OMMAND
R
EGISTER
CR3-(
N
) ............................................................................................................ 31
2.4 T
HE
T
RANSMIT
P
ULSE
S
HAPING
C
IRCUITRY
.................................................................................... 31
Figure 19.The Bellcore GR-499-CORE Transmit Output Pulse Template for DS3 Applications .................... 32
Figure 20.The Bellcore GR-253-CORE Transmit Output Pulse Template for SONET STS-1 Applications ... 33
Enabling the Transmit Line Build-Out Circuit ..................................................................................... 33
C
OMMAND
R
EGISTER
, CR1-(
N
) ........................................................................................................... 33
Disabling the Transmit Line Build-Out Circuit .................................................................................... 33
C
OMMAND
R
EGISTER
, CR1-(
N
) ........................................................................................................... 34
Design Guideline for Setting the Transmit Line Build-Out Circuit ...................................................... 34
The Transmit Line Build-Out Circuit and E3 Applications .................................................................. 34
2.5 I
NTERFACING THE
T
RANSMIT
S
ECTIONS OF THE
XRT73L04A
TO THE
L
INE
...................................... 34
Figure 21.Recommended Schematic for Interfacing the Transmit Section of the XRT73L04A to the Line .... 34
T
RANSFORMER
R
ECOMMENDATIONS
.................................................................................................... 35
3.0 THE RECEIVE SECTION ......................................................................................................................... 36
3.1 I
NTERFACING THE
R
ECEIVE
S
ECTIONS OF THE
XRT73L04A
TO THE
L
INE
........................................ 36
Figure 22.Recommended Schematic for Interfacing the Receive Section of the XRT73L04A to the Line (Trans-
former-Coupling) .............................................................................................................................. 36
Figure 23.Recommended Schematic for Interfacing the Receive Section of the XRT73L04A to the Line (Capac-
itive-Coupling) .................................................................................................................................. 36
3.2 T
HE
R
ECEIVE
E
QUALIZER
B
LOCK
................................................................................................... 37