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XRT73L04B
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

REV. 1.0.1

2

TYPICAL APPLICATIONS

TRANSMIT INTERFACE CHARACTERISTICS:

• Accepts either Single-Rail or Dual-Rail data from 

Terminal Equipment and generates a bipolar signal 
from the line

• Integrated Pulse Shaping Circuit

• Built-in B3ZS/HDB3 Encoder (which can be dis-

abled)

• Contains Transmit Clock Duty Cycle Correction  

Circuit on-chip

• Generates pulses that comply with the ITU-T G.703 

pulse template (E3 applications)

• Generates pulses that comply with the DSX-3 pulse 

template as specified in Bellcore GR-499

-CORE

 

and ANSI T1.102_1993

• Generates pulses that comply with the STSX-1 

pulse template as specified in Bellcore GR-253-
CORE

• Transmitter can be turned off in order to support 

redundancy designs

RECEIVE INTERFACE CHARACTERISTICS:

• Integrated Adaptive Receive Equalization (optional) 

and Timing Recovery

• Declares and Clears the LOS defect per ITU-T 

G.775 requirements (E3 and DS3 applications)

• Meets Jitter Tolerance Requirements as specified 

in ITU-T G.823_1993 (E3 Applications)

• Meets Jitter Tolerance Requirements as specified 

in Bellcore GR-499-CORE (DS3 Applications)

• Declares Loss of Signal (LOS) and Loss of Lock 

(LOL) Alarms

• Built-in B3ZS/HDB3 Decoder (which can be dis-

abled)

• Recovered Data can be muted while the LOS Con-

dition is declared

• Outputs either Single-Rail or Dual-Rail data to the 

Terminal Equipment

• Receiver can be powered down in order to con-

serve power in redundancy designs

F

IGURE

 2.  M

ULTI

C

HANNEL

 ATM A

PPLICATION

ATM

Switch/

SAR

XRT74L74

RPOS

RNEG

RxLineClk

XRT71D04

XRT73L04B

RRPOS
RRNEG
RRClk

RPOS

RNEG

RxClk

RPOS
RNEG
RxClk

RTIP

RRing

TTIP

TRing

TPOS

TNEG

TxLineClk

MClk

TPOS
TNEG
TxClk

4 Channel E3/DS3 ATM

UNI

4 Channel E3/DS3 J/A

4 Channel E3/DS3 LIU

F

IGURE

 3.  M

ULTI

S

ERVICE

 - F

RAME

 R

ELAY

 A

PPLICATION

Frame

Relay

XRT72L58

RPOS
RNEG

RxLineClk

XRT71D04

XRT73L04B

RRPOS
RRNEG
RRClk

RPOS

RNEG

RxClk

RPOS
RNEG
RxClk

RTIP

RRing

TTIP

TRing

TPOS

TNEG

TxLineClk

MClk

TPOS
TNEG
TxClk

8 Channel E3/DS3 Framer

2 x 4 Channel E3/DS3 J/A

2 x 4 Channel E3/DS3 LIU

Содержание XRT73L02MIV-F

Страница 1: ...f Line Code Violations FEATURES Incorporates an improved Timing Recovery circuit and is pin and functional compatible to XRT73L04A Meets E3 DS3 STS 1 Jitter Tolerance Require ments Contains a 4 Wire M...

Страница 2: ...irements E3 and DS3 applications Meets Jitter Tolerance Requirements as specified in ITU T G 823_1993 E3 Applications Meets Jitter Tolerance Requirements as specified in Bellcore GR 499 CORE DS3 Appli...

Страница 3: ...DMO_1 TxAVDD_1 TNData_1 TPData_1 TxClk_1 TxAGND_0 TRing_0 TxAVDD_0 TTIP_0 MTIP_0 MRing_0 E3_2 E3_3 STS1 DS3_2 LLB_2 RLB_2 RxAVDD_2 RRing_2 RTIP_2 RxAGND_2 REQEN_2 STS1 DS3_3 LLB_3 RLB_3 RxAVDD_3 RRing...

Страница 4: ...s typical channel 17 Figure 6 Timing Diagram of the Transmit Terminal Input Interface 17 Figure 7 Timing Diagram of the Receive Terminal Output Interface 17 Line Side Parameters E3 Application 18 Tran...

Страница 5: ...YCLE ADJUST CIRCUITRY 29 2 3 THE HDB3 B3ZS ENCODER BLOCK 29 B3ZS Encoding 29 Figure 17 An Example of B3ZS Encoding 30 HDB3 Encoding 30 Figure 18 An Example of HDB3 Encoding 30 Disabling the HDB3 B3ZS...

Страница 6: ...is being Declared 42 COMMAND REGISTER CR3 N 43 3 6 ROUTING THE RECOVERED TIMING AND DATA INFORMATION TO THE RECEIVING TERMINAL EQUIPMENT 43 Routing Dual Rail Format Data to the Receiving Terminal Equ...

Страница 7: ...SMIT ALL ONES FEATURE 51 5 0 THE MICROPROCESSOR SERIAL INTERFACE 51 5 1 DESCRIPTION OF THE COMMAND REGISTERS 51 COMMAND REGISTER CR1 N 51 Table 7 Hexadecimal Addresses and Bit Formats of XRT73L04B Com...

Страница 8: ...a_ n and TNData_ n input pins on either the rising or falling edge of TxClk_ n 41 29 140 8 TPData_0 TPData_1 TPData_2 TPData_3 I Transmit Positive Data Input Channel n The XRT73L04B samples this pin o...

Страница 9: ...1 if the cable length between the Cross Connect and the transmit output of Channel n is greater than 225 feet 2 Set this input pin to 0 if the cable length between the Cross Connect and the transmit o...

Страница 10: ...n inputs Line Code Violation When CS SR DR is set High Single Rail operation the B3ZS HDB3 Encoder Decoder is activated and the Line Code Violation signal is out put on this pin b Operating in the HO...

Страница 11: ...gures the Receive Section of all Chan nels to invert their RxClk_ n clock output signals Setting this pin Low configures Channel n to output the recovered data via the RPOS_ n and RNEG_ n output pins...

Страница 12: ...t pins NOTE This input pin functions as the CS input pin if the XRT73L04B device has been configured to operate in the HOST Mode 72 71 108 107 E3_0 SDO E3_1 SDI E3_2 E3_3 I O I I I E3_Mode Select Chan...

Страница 13: ...r in order to check for line driver failure This pin is internally pulled High 48 26 133 11 DMO_0 DMO_1 DMO_2 DMO_3 O Drive Monitor Output Channel n If no transmitted AMI signal is present on MTIP_ n...

Страница 14: ...g the LOSTHR pin to GND or VDD provides two settings This pin must be set to a High or Low level upon power up and should not be changed during operation This pin is only applicable during DS3 or STS...

Страница 15: ...on whether the XRT73L04B is oper ating in the HOST Mode or in the Hardware Mode HOST Mode Operation Chip Select Input The Local Microprocessor must assert this pin to 0 in order to enable communicatio...

Страница 16: ...lling edge of the SClk input signal This pin is tri stated upon completion of data transfer 110 REGR RxClkINV I Register Reset Input Invert RxClk_ n Output Select The function of this pin depends upon...

Страница 17: ...D_0 Transmitter Analog Supply 3 3V 5 Channel n 49 TxAGND_0 Transmitter Analog Ground Channel n 50 AGND_0 Analog Ground Pin Channel n 51 RxDVDD_1 Receiver Digital Supply 3 3V 5 Channel n 56 RxDGND_1 Re...

Страница 18: ...l Clock Digital Ground 130 EXDVDDA External Clock Digital Supply 132 TxAGND_2 Transmitter Analog Ground Channel n 134 TxAVDD_2 Transmitter Analog Supply 3 3V 5 Channel n POWER AND GROUND PINS PIN NAME...

Страница 19: ...to pins with pull up or pull down resistors ABSOLUTE MAXIMUM RATINGS Storage Temperature 65 C to 150 C Operating Temperature 40 C to 85 C Supply Voltage Range 0 5V to 3 465V Theta JA 24 C W Theta JC 5...

Страница 20: ...0 TxClk_ n Frequency SONET STS 1 51 84 MHz TxClk_ n Frequency DS3 44 736 MHz TxClk_ n Frequency E3 34 368 MHz tRTX TxClk_ n Clock Rise Time 10 to 90 3 5 ns tFTX TxClk_ n Clock Fall Time 90 to 10 3 5 n...

Страница 21: ...MING DIAGRAM OF THE TRANSMIT TERMINAL INPUT INTERFACE R1 31 6 R2 31 6 Channel n Channel n TxPOS_ n TxNEG_ n TxLineClk_ n TTIP_ n TRing_ n TPData_ n TNData_ n TxClk_ n Only One Channel Shown 1 1 R3 75...

Страница 22: ...s Transmit Output Pulse Width Ratio 0 95 1 00 1 05 Transmit Output Jitter with jitter free input TxClk_ n 0 02 0 05 UIpp Receive Line Characteristics Receive Sensitivity Length of cable 1200 1400 feet...

Страница 23: ...ured with TxLEV 1 0 90 1 00 1 10 Vpk Transmit Output Pulse Width 8 6 9 65 10 6 ns Transmit Output Pulse Amplitude Ratio 0 90 1 00 1 10 Transmit Output Jitter with jitter free input TxClk_ n 0 02 0 05...

Страница 24: ...feet TxLEV 1 0 90 1 00 1 10 Vpk Transmit Output Pulse Width 10 10 11 18 12 28 ns Transmit Output Pulse Amplitude Ratio 0 90 1 00 1 10 Transmit Output Jitter with jitter free input TxClk_ n 0 02 0 05...

Страница 25: ...PUT PULSE TEMPLATE FOR E3 APPLICATIONS 0 50 V 100 14 55ns Nominal Pulse 12 1ns 14 55 2 45 17 ns 14 55 2 45 8 65 ns 10 10 20 FIGURE 9 BELLCORE GR 499 CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR DS3 APPLICA...

Страница 26: ...PULSE TEMPLATE FOR SONET STS 1 APPLICATIONS STS 1 Pulse Template 0 2 0 0 2 0 4 0 6 0 8 1 1 2 1 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 1 1 1 2 1 3 1 4 Time in UI No...

Страница 27: ...of SClk Setup Time 5 ns t24 SDI to Rising Edge of SClk Hold Time 5 ns t25 SClk Low Time 65 80 ns t26 SClk High Time 65 80 ns t27 SClk Period 160 ns t28 CS Low to Rising Edge of SClk Hold Time 5 ns t2...

Страница 28: ...sig nals via the RPOS_ n RNEG_ n and RxClk_ n output pins THE MICROPROCESSOR SERIAL INTERFACE The XRT73L04B can be configured to operate in ei ther the Hardware Mode or the HOST Mode The XRT73L04B con...

Страница 29: ...r should refer toTable 2 to determine the appropriate Address for each command register of each channel in the XRT73L04B The command register description re fers to CR x n where x 0 to 7 and n refers...

Страница 30: ...RLOS_1 ALOS_1 DLOS_1 DMO_1 0x09 CR1 1 R W TxOFF_1 TAOS_1 TxClkINV_1 TxLEV_1 Reserved 0x0A CR2 1 R W Reserved Reserved ALOSDIS_1 DLOSDIS_1 REQEN_1 0x0B CR3 1 R W SR DR _1 LOSMUT_1 RxOFF RxClk_1INV Res...

Страница 31: ...0x19 CR1 3 R W TxOFF_3 TAOS_3 TxClkINV_3 TxLEV_3 Reserved 0x1A CR2 3 R W Reserved Reserved ALOSDIS_3 DLOSDIS_3 REQEN_3 0x1B CR3 3 R W SR DR _3 LOSMUT_3 RxOFF RxClk_3INV Reserved 0x1C CR4 3 R W Reserv...

Страница 32: ...ing information from the Terminal Equipment 2 1 1 Accepting Dual Rail Data from the Termi nal Equipment Whenever the XRT73L04B accepts Dual Rail data from the Terminal Equipment it does so via the fol...

Страница 33: ...e Terminal Equipment 2 2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIR CUITRY The on chip Pulse Shaping circuitry within the Trans mit Section of each Channel in the XRT73L04B gen erates pulses of the appr...

Страница 34: ...four consecutive zeros then it substitutes these four 0 s with either a 000V or a B00V pattern The HDB3 Encoder decides whether to substitute with ei ther the 000V or the B00V pattern in order to in s...

Страница 35: ...ld to High or Low The purpose of the Transmit Line Build Out circuit is to permit config uration of each channel to transmit an output pulse which is compliant to either of the following pulse templat...

Страница 36: ...t If the Transmit Line Build Out circuit is disabled then the XRT73L04B outputs partially shaped pulses onto the line via the TTIP_ n and TRing_ n output pins Disable the Transmit Line Build Out circu...

Страница 37: ...output pins The cable loss that these pulses experience over long cable lengths e g greater than 225 feet cause these pulses to be properly shaped and comply with the appropriate pulse template requir...

Страница 38: ...ty CA 94063 Tel 650 568 5800 FAX 650 568 6165 Email info haloelectronics com Website http www haloelectronics com Transpower Technologies Inc Corporate Office Park Center West Building 9805 Double R B...

Страница 39: ...ipment 3 1 INTERFACING THE RECEIVE SECTIONS OF THE XRT73L04B TO THE LINE The design of the Receive Circuitry should be trans former coupled to the Receive Section to the line The specification documen...

Страница 40: ...nsmitting Terminal is NOT known For DS3 STS 1 and E3 applications enable the Receive Equalizer by setting either the REQEN_ n input pin high or the REQEN_ n bit field to 1 The remain der of this secti...

Страница 41: ...stallation it is recommended that the Receive Equalizer of the XRT73L04B be enabled by pulling the REQEN_ n input pins High or by setting the REQEN_ n bit fields to 1 NOTE The results of extensive tes...

Страница 42: ...the Near End Receiving Terminal However once the data has made it across the E3 DS3 or STS 1 Trans port Medium and has been recovered by the Clock Recovery PLL it is now necessary to restore the orig...

Страница 43: ...tains circuitry that monitors the fol lowing two parameters associated with the incoming line signals 1 The amplitude of the incoming line signal via the RTIP and RRing inputs 2 The number of pulses d...

Страница 44: ...4B was designed to meet the ITU T G 775 specification timing requirements for declaring and clearing the LOS indicator In particular a chan nel declares an LOS between 10 and 255 UI or E3 bit periods...

Страница 45: ...S threshold amplitudes Declaring ALOS A channel n declares ALOS_ n whenever the ampli tude of the receive line signal falls below the Signal Level to Declare ALOS levels as specified inTable 5 Clearin...

Страница 46: ...10 1 s e g average pulse density of greater than 33 Monitoring the State of DLOS If the XRT73L04B is operating in the HOST Mode the state of DLOS_ n of Channel n can be polled or monitored by reading...

Страница 47: ...ROUTING THE RECOVERED TIMING AND DATA INFORMATION TO THE RECEIVING TERMINAL EQUIPMENT Each channel ultimately takes the Recovered Timing and Data information converts it into CMOS levels and routes i...

Страница 48: ...data to the Receiving Terminal Equipment This feature may be useful for those cus tomers whose Receiving Terminal Equipment logic design is such that the RPOS_ n and RNEG_ n da ta must be sampled on...

Страница 49: ...pins as illustrat ed in Figure 31 and Figure 32 b Operating in the Hardware Mode The XRT73L04B is configure to output Dual Rail data from the Receive Sections of all channels by pulling the SR DR pin...

Страница 50: ...power This feature can permit powering down the Receive Section of the LIU s on the Secondary Line Card which reduces their power consumption by approximately 80 a Operating in the Hardware Mode Shut...

Страница 51: ...hannel After this post Loop Back data has been processed through the Receive Section it out puts to the Near End Receiving Terminal Equipment via the RPOS_ n RNEG_ n and RxClk_ n output pins Figure 33...

Страница 52: ...nfigured to operate in the Digital Local Loop Back Mode Configure a channel to operate in the Digital Local Loop Back Mode by employing either one of the fol lowing two steps a Operating in the Host M...

Страница 53: ...de Configure a channel to operate in the Remote Loop Back Mode by employing either one of the following two steps a Operating in the HOST Mode To configure Channel n to operate in the Remote Loop Back...

Страница 54: ...it fields via the Micro processor Serial Interface Table 6 presents a Truth Table which relates the set ting of the TxOFF external pin and bit field for a chan nel to the state of the Transmitter This...

Страница 55: ...Operating in the Hardware Mode Configure Channel n to transmit an all 1 s pattern by toggling the TAOS_ n input pin pin 45 46 135 or 136 High Terminate the all 1 s pattern by tog gling the TAOS_ n inp...

Страница 56: ...1 RLOS_1 ALOS_1 DLOS_1 DMO_1 0x09 CR1 1 R W TxOFF_1 TAOS_1 TxClkINV_1 TxLEV_1 Reserved 0x0A CR2 1 R W Reserved Reserved ALOSDIS_1 DLOSDIS_1 REQEN_1 0x0B CR3 1 R W SR DR_1 LOSMUT_1 RxOFF RxClk_1INV Res...

Страница 57: ...ring an LOS Condition Bit D2 ALOS_ n Analog Loss of Signal Status Channel n This Read Only bit field indicates whether or not the Channel n Analog LOS Detector is currently declar ing an LOS condition...

Страница 58: ...of TxClk Writing a 0 to this bit field con figures the Transmitter to sample the TPData and TNData input pins on the falling edge of TxClk Bit D1 TxLEV_ n Transmit Line Build Out En able Disable Sele...

Страница 59: ...locks NOTE This Encoder Decoder performs HDB3 Encoding Decoding if the XRT73L04B is operating in the E3 Mode Otherwise it performs B3ZS Encoding Decoding Writing a 1 to this bit field also configures...

Страница 60: ...used to configure Channel n to operate in any one of a va riety of Loop Back modes Table 8 relates the contents of LLB_ n and RLB_ n and the corresponding Loop Back mode for Chan nel n 5 3 OPERATING...

Страница 61: ...point reading the data contents of the addressed Com mand Register at Address A4 A3 A2 A1 A0 via the SDO output pin can begin The Microprocessor Serial Interface outputs this five bit data word D0 thr...

Страница 62: ...S3 E3 STS 1 LINE INTERFACE UNIT REV 1 0 1 58 FIGURE 38 TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE SDI R W A1 A0 CS SCLK CS SCLK SDI SDO D0 D1 D2 D7 t22 t21 t23 t24 t25 t26 t27 t28 t29 t30...

Страница 63: ...The control dimension is the millimeter column 144 LEAD QUAD FLAT PACK 20 x 20 x 1 4 mm LQFP rev 1 00 A2 L C e 108 73 72 37 109 144 D D1 D D1 1 36 B A1 A Seating Plane SYMBOL MIN MAX MIN MAX A 0 055 0...

Страница 64: ...in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys tem or to significantly affect its safety or effective...

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