Eurotech CPU-1450, Руководство пользователя, Страница: 12 / 43

CPU-1450 SPM block diagram architecture 12
System Power Planes
The system has several independent power planes, as described in the following table.
Note that when a particular power plane is shut off, it should go to a 0V level.
Plane Controlled by Description
MAIN SLP_S3# signal
When SLP_S3# goes active (low), power is shut off to any circuit not required to wake the
system. Since the ACPI standard S3 state requires that the memory context be preserved,
power should be retained to the main memory. However the CPU-1450 does not support the
Suspend-to-Ram, so the main memory is shutdown together with the main plane.
The processor, main memory, devices on the PCI bus, LPC interface, downstream hub
interface and AGP will typically be shut off when the Main power plane is shut, although
there may be small subsections powered.
RESUME Always present
In this plane there are the ICH2 resume logic, Ethernet controller and others individual
subsystems used for power management. This plane is powered from +5VSB OR +3V3SB.
Please refer
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Table 2. System power planes
Power Management interface signals
The power management may be entered or exited depending on some specific signals listed in Table 3:
Name Type Description
SLP_S3# Internal
Power plane control. This signal is used to shut off power to all non-critical systems when in S3
(Suspend To RAM), S4 (Suspend to Disk) or S5 (Soft Off) states
PWRBTN# Input
The Power Button will cause SMI# or SCI to indicate a system request to go to a sleep state. If the
system is already in a sleep state, this signal will cause a wake event.
If PWRBTN# is pressed for more than 4 seconds, this will cause an unconditional transition (power
button override) to the S5 state with only the PWRBTN# available as a wake event. Override will
occur even if the system is in the S1-S4 states. This signal has an internal pull-up resistor.
RI# Input
From the modem interface. This signal can be enabled as a wake event; this is preserved across
power failures.
PSON# or ATX_ON Output Power-On command to ATX Power supply. When PSON# is low the ATX power supply is turned on.
VDD Input Main power from the ATX Power supply. It can be shut off from power management controller.
+5VSB Input
+5 Volts-Always from the ATX Power supply. It is never shut off unless the user turns off a
mechanical switch.
Table 3. Power management for interface signals
An0065. CPU-1450 Soft Power Management
In the rest of this document we will analyse the signals considering the related programming activities.