Schematic Diagrams
B - 18 Clock Generator
B.Schematic Diagrams
Clock Generator
Sheet 17 of 37
Clock Generator
3.3VS
3. 3 VS
1.0 5VS
3.3VS
C LK_PC IE_I CH # 13
3. 3 VS
5,8, 9, 1 0, 11, 12, 13, 14, 15 , 18 ,19 ,2 0,2 1,2 2,2 3,24, 25, 29
C LK_MC H _B CL K# 4
C LK_CP U_BC L K 2
C LK_DR EFS S 5
C LK_PC IE_I CH 1 3
C LK_DR EF 5
C LK_DR EFS S# 5
C LK_CP U_BC L K# 2
C LK_DR EF# 5
C LK_MC H _B CL K 4
W LAN _C L KR EQ # 19 ,2 3
C L K_ BSEL 0
2 ,4
C LK _I C H4 8
1 4
C L K_ BSEL 1
2 ,4
C L K_ BSEL 2
2 ,4
C LK _I C H1 4
1 4
PM_S TP PCI #
1 4
PM_S TPC PU #
1 4
PC LK_K BC
2 2
C LK_PW RG D
14
IC H _S MBC LK0
10 ,11, 1 4
IC H _S MBD AT0
10 ,11, 1 4
PC LK _I C H3 3
1 3
1 . 05VS
2,3 , 4, 5,7 , 8, 12 , 15 , 27
C LK_PC IE_C R 20
C LK_SATA# 12
C LK_PC IE_C R# 2 0
C LK_PC IE_3 GP LL # 5
C LK_PC IE_3 GP LL 5
C LK_SATA 12
C LK_PC IE_MIN I # 19
C LK_PC IE_MIN I 19
MC H _C LKR EQ# 5
C LK_PC IE_MIN I _3 G # 23
C LK_PC IE_MIN I _3 G 2 3
SATA_CLKR EQ #
1 4
N EW _C LKR EQ#
1 9
C LK_PC IE_L AN 23
C LK_PC IE_L AN # 23
C LK_PC IE_N EW _C AR D # 19
C LK_PC IE_N EW _C AR D 19
PC LK_TPM
1 9
C LK_CP U_BC LK#
C LK_DR EF SS
C LK_DR EF #
C LK_DR EF
C LK_PC IE_ I CH
C LK_MC H _ BC LK
C LK_CP U_BC LK
C LK_PC IE_ I CH #
C LK_MC H _ BC LK#
C LK_DR EF SS#
C L K_B SEL 0
C L K_I C H 48
C L K_B SEL 1
C L K_B SEL 2
C L K_I C H 14
PC LK_KBC
PC LK_IC H 33
C LK_PC IE_ 3G PLL
C LK_PC IE_ C R
C LK_PC IE_ 3G PLL#
C LK_PC IE_ C R #
C LK_SATA
C LK_SATA#
C LK_PC IE_ MIN I
C LK_PC IE_ MIN I #
C LK_PC IE_ MIN I _3G
C LK_PC IE_ MIN I _3G #
C LK_PC IE_ LAN #
C LK_PC IE_ LAN
C LK_PC IE_ N EW _CA RD #
C LK_PC IE_ N EW _CA RD
XTAL_I N
XTAL_O U T
PC LK_TP M
C 411
0. 1 U_ 10V _X7R_0 4
C 44 4
0 .1U _1 0V_X7R _0 4
R61
2. 2K_0 4
C 412
0 .1U _1 0V_X7R_0 4
C 136
1 U _6. 3V_ 04
C 42 2
0 .1U _1 0V_X7R _04
X1
FS X8L _14 .3 18MH z
1
2
3
4
L 4
H CB 160 8KF -1 21T2 5
R70
10K_04
C 12 5
1 0U _6. 3V_0 8
R68
33_ 04
C 9 1
10 U_ 6.3 V_ 08
C10 8
1U _ 6. 3 V_ 04
C 428
0. 1 U_ 10V _X7R_0 4
R 40
475 _1% _04
C 44 0
0. 1 U _10 V_X7R_0 4
C 445
0 . 1U _ 10V_X7R _04
C 43 1
1 U _ 6. 3V _04
C 41 9
1U _ 6. 3V _04
U1
SLG 8S P510 T
5
9
61
37
51
53
43
50
54
8
11
7
63
49
62
10
26
48
60
59
42
44
39
3
4
20
55
64
6
1
15
16
23
52
45
46
22
21
30
31
35
34
33
32
18
17
13
14
56
36
12
2
19
29
41
40
27
28
24
25
58
38
47
57
P CI 3
VD
D
4
8
VD
D
R
EF
C PU _STOP#
CP U1
C PU 0#
S RC 7 #/ C R #_E
C PU 1#
CP U0
G
N
DP
CI
GN
D
4
8
P CI F5/I TP_E N
S DATA
VD
D
C
P
U
_
I
O
R EF0 / FSL C /ES T_SEL
U SB_ 48MH z/ FSLA
VD
D
S
R
C
_
IO
1
N C
X1
X2
G
N
DS
RC
3
SR C 7/ C R #_F
VD
D
S
R
C
P CI 1 /C R #_ B
P CI 2 /TME
V
D
D
P
LL3
_I
O
VD
D
C
PU
S CLK
P CI 4 /27_Sele ct
P CI 0 /C R #_ A
GN
D
VD
D
P
L
L
3
GN
D
S
R
C
1
GN
D
C
P
U
VD
D
S
R
C
_
IO
3
S RC 8 #/ I TP#
SRC 2 #/SA TA#
SR C 2/ SATA
SR C9
SR C 9#
S RC 10#
SR C 10
SR C 11 / CR # _H
SR C 11# / CR # _G
27MH z_S S/S RC 1 #/ SE2
2 7MH z_N on SS/ SR C 1/ SE1
S RC 0/D O TT_96
SR C0 #/D O TC _96
C K_PW R GD / PD #
VD
D
S
R
C
_
I
O
2
VD
D
_
IO
V
D
DP
CI
GN
D
G
N
DS
RC
2
SR C6
SR C 6#
SR C4
SR C 4#
SR C3 / CR # _C
SR C 3# / CR # _D
GN
D
R
E
F
P CI _ STOP#
SR C8/ ITP
F SLB /TEST_MO D E
C 1 68
2 2P_5 0V_04
R64
10K_04
R73
10K_04
C 435
0.1U _1 0V_X7 R_ 04
R84
4 75_ 1% _0 4
R76
*10K_0 4
R82
4 75_ 1% _0 4
L2
H C B1 608 KF-121 T25
R78
10K_04
R80
*10K_0 4
C 1 67
22 P_ 50 V_ 04
R31 6
*33_ 04
R75
33_ 04
R 41
475 _1% _04
R71
33_ 04
C 42 6
0. 1U_1 0V _X7R_04
R74
33_ 04
CLOCK GENERATOR
166 MHz
CK505
BSEL2
667 MHz
0
200 MHz
266 MHz
0
BSEL0
0
40m ils
800 MHz
0
FSLB
0
1
Frequency
BSEL1
Host Clock
0
FSLC
1
1
FSLA
1066 MHz
40mi ls
PL ACE CRYS TAL WIT HIN
50 0 MI LS O F
SL G8SP 510T
La yout not e:
Z o=55 Oh m
Z o=55 Oh m
SL Zdiff=100 Ohm
MS Zdiff=95 Ohm
9LPRS365
FSLA
FSLB
FSLC
CR# _A( SAT A_C LKR EQ# ) - -> SRC 2/2 # - -> CL K_S ATA
CR# _B( NEW _CL KRE Q#) - -> SRC 4/4 # - -> CL K_P CIE _NE W_C ARD
CR# _H( MCH _CL KRE Q#) - -> SRC 10/ 10# - -> CLK _PC IE_ 3GP LL
CR# _G( WLA N_C LKR EQ# ) - -> SRC 9/9 # - -> CL K_P CIE _MI NI
0 = PI N 46 /47 as SRC_ 8
1 = PI N 46 /47 as CPU_ ITP
0 = Pi n 13 /14 as DOT9 6, 17/1 8 as LC D_CL K
1 = Pi n 13 /14 as SRC_ 0, 17/1 8 as 27 M/27 MSS
P in- 7
P in- 6
RTM875T-606-VD-GR
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