3: BIOS Setup Utility
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CPU to PCI Write
Buffer
When enabled, up to four words of data can be
written to the PCI bus without interrupting the
CPU. When disabled, a write buffer is not used
and the CPU read cycle will not be completed until
the PCI bus signals that it is ready to receive the
data.
PCI Dynamic
Bursting
When enabled, every write transaction goes to the
write buffer. “Burstable” transactions then burst
on the PCI bus and “nonburstable” transactions do
not.
PCI Master 0 WS
Write
When enabled, writes to the PCI bus are executed
with zero wait states.
PCI Delay
Transaction
The chipset has an embedded 32-bit posted write
buffer to support delay transactions cycles. Enable
to support compliance with PCI specification
version 2.1.
PCI#2 Access #1
Retry
When enabled, the AGP Bus (PCI#1) access to
PCI Bus (PCI#2) is executed with the error retry
feature.
AGP Master 1 WS
Write
This implements a single delay when writing to the
AGP Bus. By default, two-wait states are used by
the system, allowing for greater stability.
AGP Master 1 WS
Read
This implements a single delay when reading to
the AGP Bus. By default, two-wait states are used
by the system, allowing for greater stability.
Memory
Parity/ECC Check
Enable this item to allow BIOS to perform a
parity/ECC check to the POST memory tests.
Enable only if the system DRAM supports
parity/ECC checking.
