ETAS
Hardware Description
FETK-S2.1 - User’s Guide
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4
Hardware Description
In this chapter, the function blocks of the FETK-S2.1 are explained in detail.
4.1
Architecture
Fig. 4-1 shows the block diagram of the FETK-S2.1.
Fig. 4-1
FETK-S2.1 Architecture
While the microcontroller accesses the program data (not the program code)
out of the data emulation memory provided by the microcontroller, the content
of the data emulation memory can simultaneously be modified by the calibra-
tion and development system through the FETK Ethernet interface. This pro-
cess enables adjustments of parameters, characteristic lines and maps
through the calibration and development system. Using an additional measure-
ment data memory area, the ECU microcontroller can provide data to the cali-
bration and development system by buffering the data (DISTAB17) and
triggering the FETK to read the data via JTAG or LFAST. The FETK then reads,
buffers, processes and sends this measured data to the PC.
If no additional measurement data memory is available, the FETK-S2.1 can
alternatively read the data to be measured directly from the microcontroller’s
memory. This process is Triggered Direct Measurement (TDM) with DISTAB17.
The 100/1000 Mbit/s FETK Ethernet interface provides communication with
the PC.
FETK Connector Description
CON1
ECU Interface
CON2
Power supply
CON3
Ethernet interface (ES89x module
Tool
Interface
Trigger
Unit
Control
Unit
Interface
to
ECU
Automatic
Power
‐
On
FETK
Interface
1
Gbit/s
Power
Supply
Monitoring
ECU
Reset
&
Power
Control
ECU
Reset
Ethernet
Phy
Ethernet
Traffic
Detection
Sense
ECU
Voltage
ECU
Debug
Interface
Configu
‐
ration
Flash
UBatt
ECU
ED
‐
RAM,
Interface
Supply
CAL
Wakeup
Debug
Power
Power
Supply
Standby
Power
Supply
