ETK-V1.1 - User’s Guide
28
ETAS
Hardware Description
4.12.2
Braindead Flashing via Chip Select Remapping
BDF via chip select remapping is only supported for compatibility reasons. The
following limitations apply:
1. Works only with MPC55554 microcontrollers.
2. /CS0 signal must not be used by any memory device on the ECU during
BDF.
3. Boot configuration signals BOOTCFG[1:0], RSTCFG and PLLCFG[1..0]
must be configured properly (see notes below).
For new projects, BDF via JTAG debug interface (see chapter 4.12.1 on page 27)
shall be used instead.
When BDF via chip select remapping is initiated, the ETK-V1.1 forces the ECU's
microcontroller into reset. The ETK memory is mapped to chip select signal /CS0.
A flash programming driver is downloaded into the ETK memory. The ETK drives
the BOOTCFG[1:0] inputs to configure the ECU's microcontroller to external
boot. Upon reset is deasserted, the RSTCFG pin is driven low in order to force the
microcontroller to accept the external reset configuration presented on
BOOTCFG[1:0]. The ECU's microcontroller boots from /CS0 (which is now the
ETK chip select) and executes the flash programming driver from the ETK mem-
ory. The driver receives data via the ETK mailbox and programs it into the internal
microcontroller flash. When flash programming is done, the microcontroller
must be forced into reset again and the changes done before must be reverted.
When reset is released next time, the microcontroller takes its reset configuration
from the ECU and boots from the standard boot memory (i.e. internal Flash) to
execute the recently programmed code.
Note
When flashing an MPC5534 microcontroller, please ensure that your flash pro-
gramming driver sets the JTAG access priority to internal SRAM higher than the
priority for opcode fetches from internal SRAM (MPC5534 Crossbar register
XBAR_MPR3
). ETAS suggests to set
XBAR_MPC3
to the value
0x00000213
.
When using the default priority for JTAG accesses, the ProF flow may fail as the
ETK does not always gets access to the microcontrollers SRAM. See the
MPC5534 reference manual section XBAR for details.
Note
To avoid bus contentions when the ETK drives the Reset Configuration the
BOOTCFG[1:0] bus and the RSTCFG signal of the microcontroller must not be
hard-wired to VCC or GND or driven by a strong driver. Instead, the bus must
either be driven by a driver that is disabled when the ETK is driving the reset
configuration or by weak pull-up or pull-down resistors.
Note
As the microcontroller's FMPLL mode selection signals PLLCFG[1:0] are not
driven by the ETK-V1.1, they must be driven to appropriate voltage levels by
the ECU during brain dead flashing. Refer to the microcontroller's reference
manual for details.
