Technical Data
6.3 FPGA
Type
Altera Cyclone V GX, FBGA 484, 50K LE CGXFC4C7F23C8N
IP-core
Beckhoff
®
IP-core
- contains 60 kByte ESC DPRAM
- supports 64 bit timestamps (for DC, Sync and Latch values)
- supports 8 EtherCAT SyncManagers
- supports 8 EtherCAT FMMUs
Table 5:
FPGA
6.4 XMC Interface
PCIe endpoint
FPGA
PCIe port
according to PCI Express Specification R1.0a
Lanes
Up to Quad Lane PCIe Link
Form factor
VITA 42.3 (XMC)
Mode
as device
Connector
via XMC P15 and P16
Device ID / Vendor ID
constant, 0x0703 / 0x12FE
Subsystem Device ID /
Subsystem Vendor ID
0x0703 /
0x12FE as endpoint
Revision ID
0x0001
Class Code
0x28000
Table 6:
Data of the XMC interface
6.5 Ethernet Interface
Number
1
Standard
100BASE-TX, 100Mbit/s according to IEEE 802.3
Controller
EtherCAT Slave Controller Beckhoff IP Core integrated in FPGA
+ 2x MII Phy (Micrel KSZ8081MNX)
Electrical isolation
via transformer,
2.5 mm creepage distance,
1500 Vrms / 2250 VDC
Ports
IN and OUT
Connector
2 x RJ45 socket with separate LEDs for status indication (see “LED
Indication” page 15)
Table 7:
Data of the EtherCAT interface
Page 20 of 27
Hardware Manual • Doc. No.: E.1102.21 / Rev. 1.3
ECS-XMC/FPGA
