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Connector Assignments

Page 26 of 28

Hardware Manual Doc.-Nr.: E.1108.21 /Rev. 1.0

ECS-CPCIs/FPGA

See

Figure 7:

PCB top view of ECS-CPCIs/FPGA on page 15 for the position of the pins.

Pin

Signal

Direction

3V3

TDI

Input

TDO

Output

TCK

Input

TMS

Input

GND

5.3 JTAG FPGA (X1300)

Содержание ECS-CPCIs/FPGA

Страница 1: ...Hannover Germany http www esd eu Phone 49 0 511 3 72 98 0 Fax 49 0 511 3 72 98 68 ECS CPCIs FPGA Hardware Manual Doc Nr E 1108 21 Rev 1 0 Page 1 of 28 ECS CPCIs FPGA CompactPCI Serial to EtherCAT Slave Interface Hardware Manual to Products E 1108 02 ...

Страница 2: ...tive owners Notes The information in this document has been carefully checked and is believed to be entirely reliable esd electronics makes no warranty of any kind with regard to the material in this document and assumes no responsibility for any errors that may appear in this document In particular descriptions and technical data specified in this document may not be constituted to be guaranteed ...

Страница 3: ..._en_10 docx Date of print 2022 03 04 Document type number DOC0800 Hardware version 1 0 Document History The changes in the document listed below affect changes in the hardware as well as changes in the description of the facts only Rev Chapter Changes versus previous version Date 1 0 First English manual 2022 03 04 Technical details are subject to change without further notice ...

Страница 4: ...lso include a warning relating to property damage DANGER Danger statements indicate a hazardous situation which if not avoided will result in death or serious injury WARNING Warning statements indicate a hazardous situation that if not avoided could result in death or serious injury CAUTION Caution statements indicate a hazardous situation that if not avoided could result in minor or moderate inju...

Страница 5: ...es and do not expose it to unnecessary thermal radiation Ensure an ambient temperature as specified in the technical data DANGER Hazardous Voltage Risk of electric shock due to unintentional contact with uninsulated live parts with high voltages inside of the system into which the ECS CPCIs FPGA is to be integrated Disconnect all hazardous voltages mains voltage before opening the system Ensure th...

Страница 6: ...d The operation of the ECS CPCIs FPGA for medical purposes is prohibited Service Note The ECS CPCIs FPGA does not contain any parts that require maintenance by the user The ECS CPCIs FPGA does not require any manual configuration of the hardware Unauthorized intervention in the device voids warranty claims Disposal Devices which have become defective in the long run have to be disposed in an appro...

Страница 7: ...he LEDs 16 2 3 2 LED Indication 16 2 3 2 1 Status LEDs 17 2 3 2 2 EtherCAT LEDs 17 3 Hardware Installation 18 4 Technical Data 19 4 1 1 General Technical Data 19 4 2 Hardware Components 20 4 3 FPGA 20 4 4 EtherCAT Interface 21 4 5 SYNC LATCH Interface on P3 21 4 6 User I O on P3 21 4 7 PCI Express Interface 22 4 8 Temperature Sensor 22 4 9 JTAG Interface 22 4 10Hardware ID and Serial Number 22 4 1...

Страница 8: ...le 10 Data of PCI Express Interface 22 Table 11 Data of the temperature sensor 22 Table 12 Data of JTAG interface 22 Table 13 Hardware ID and serial number 22 Table 14 Order information hardware 28 Table 15 Available manuals 28 List of Figures Figure 1 Windows Device Manager 10 Figure 2 Update Driver Software 10 Figure 3 Installing ESI to EtherCAT Workbench picture detail 12 Figure 4 Scan result s...

Страница 9: ...NIC where the EtherCAT Master will run Demo version of the EtherCAT Workbench and full version of the EtherCAT Stack object for Windows and Linux are included in delivery of ECS CPCIs FPGA Drivers are also available for the real time operating system QNX others on request The stack is also offered as source for own developments Following steps have to be performed 1 Install the ECS CPCIs FPGA into...

Страница 10: ...icture detail When you are asked where to look for the driver files select Browse my computer for driver software Select the folder that matches your operating system e g driver ECS win64 when using 64 bit Windows and click Next Figure 2 Update Driver Software 1 3 2 Linux The Linux driver for the esd EtherCAT slave device ECS CPCIs FPGA is usually delivered as source code Please refer to driver EC...

Страница 11: ...d devecs pexesc v init_driver Asked for MSI Interrupt init_driver Got MSI Interrupt 0x102 card_probe_esc ESC Type 0x04 60 kB 8 SMs 8 FMMUs The sample applications are installed as source code only Please refer to the Slave Stack manual for details on how to build it This document refers to the complex c sample This sample application contains input and output variables Input variables are set by t...

Страница 12: ...sult showing Slave 1 ECS CPCIs FPGA picture detail INFORMATION These samples show your ECS CPCIs FPGA described as Slave 1 ECS because the actions behavior described here remain compatible for all esd s EtherCAT slave devices After switching to online mode all slaves are in Pre Operational state In this state e g indicated by the orange symbol in Figure 4 no process data is exchanged Use the Free ...

Страница 13: ...more details about the steps performed here Then try to map the other variables that already exist in the application and ESI too and finally add your own variables Do not forget to update the ESI accordingly While many EtherCAT masters acquire most of the slave information needed from the xml ESI others might rely solely on EEPROM ESI The binary ESI can be created by the xml ESI e g with the Work...

Страница 14: ...an use several EtherCAT protocols like CoE FoE and EoE to communicate with this EtherCAT Slave device The ECS CPCIs FPGA comes with 36 3 3V LVTTL I O lines via the pin header connector P3 including the 4 signal lines from the EtherCAT slave controller 2x Sync and 2x Latch for system synchronization On request 16 of the LVTTL I O lines can be configured to 8 differential 2 5 V LVDS pairs The FPGA c...

Страница 15: ... 21 1 0 Page 15 of 28 Figure 7 PCB top view of ECS CPCIs FPGA NOTICE Read chapter Hardware Installation on page 18 before you start with the installation of the hardware See also page 24 for signal assignment of the connectors 2 2 PCB View with Connectors ...

Страница 16: ...s FPGA 2 3 2 LED Indication Indicator states Description blinking LED blinking cycle 200 ms on 200 ms off flickering LED blinking cycle 50 ms on 50 ms off single flash LED blinking cycle 200 ms on 1000 ms off double flash LED blinking cycle 200 ms on 200 ms off 200 ms on 1000 ms off Table 1 LED states according to ETG 1300 documentation 2 3 LEDs ...

Страница 17: ...ailed single flash EtherCAT state change because of configuration error double flash SM watchdog triggered Table 2 Description of Status LEDs 2 3 2 2 EtherCAT LEDs The Link Activity LEDs and the User LEDs U3 and U4 are integrated in the RJ45 sockets of EtherCAT ports IN and OUT LED Function Colour Indicator State Description EtherCAT Port U3 User LED3 green user defined via FPGA and driver IN L A ...

Страница 18: ...he system from the mains Make sure that no risk arises from the system into which the ECS CPCIs FPGA shall be inserted DANGER Hazardous Voltage Risk of electric shock due to unintentional contact with uninsulated live parts with high voltages Disconnect all hazardous voltages mains voltage before opening the system If the system does not have a flexible mains cable but is directly connected to mai...

Страница 19: ...PRESS FIT Type A Peripheral Slot CompactPCI Serial PC AirMax VS 10052837 101LF High Speed Modular Connectors R A HDR 96POS PRESS FIT Type A Peripheral Slot 36 single ended 3 3V FPGA I O lines including latch and sync signals from Beckhoff EtherCAT IP core Only for test and programming purposes JTAG 5 pin JTAG pin header X1300 JTAG Debugging Boundary Scan Signal Tap First time initialisation Temper...

Страница 20: ...nts Type Intel Cyclone V GX FPGA 484 IP core Beckhoff IP core contains 60 kByte ESC DPRAM supports 64 bit timestamps for DC Sync and Latch values supports 8 EtherCAT SyncManagers supports 8 EtherCAT FMMUs allows EEPROM read and write access according to ETG standards includes TwinCAT read write support Intention EtherCAT Slave Dependency None Notes The FPGA is identical to the PCIe EtherCAT Slave ...

Страница 21: ...hifted to user I O lines then Ask our sales team sales esd eu for further information Controller Integrated in FPGA Connector High Speed Modular Connector all signals on P3 For the pin assignment see chapter P3 96 Pin Header configured for LVTTL I O on page 25 Table 8 Data of SYNC LATCH interface on P3 Number 32 User I O Electrical isolation None Voltage Level and Termination 3 3V LVTTL configured...

Страница 22: ...two devices in the chain FPGA and Security PLD Devices which are not equipped are bridged with zero ohm resistors Purpose FPGA debugging Boundary Scan factory testing initial FPGA programming Controller Integrated in the devices Connector X1300 Samtec RSM 106 02 T S Table 12 Data of JTAG interface Serial number distribution The serial number is read and distributed by the software driver Hardware ...

Страница 23: ... offload the CPU from copying the output process image data into the host memory This is utilized by the esd EtherCAT Slave Stack The Stack and the included complex sample application with sample ESI is tested against the EtherCAT CTT default test set Please refer to the EtherCAT Slave Stack manual see Order Information page 28 for further information The ECS CPCIs FPGA is delivered with the esd V...

Страница 24: ...in Signal Meaning 1 Tx0 TxD Transmit Data 2 Tx0 TxD Transmit Data 3 Rx0 RxD Receive Data 4 5 6 Rx0 RxD Receive Data 7 8 S Shield Signal Description Tx0 Rx0 data lines of EtherCAT port reserved for future applications do not connect Shield case shield connected with the front panel of the ECS CPCIs FPGA NOTICE Permissible cable types Cables of category 5 or higher must be used to grant the function...

Страница 25: ...LVTTL1_IO_6 AA10 H6 I6 LVTTL1_IO_7 Y9 LVTTL1_IO_8 Y10 A7 B7 LVTTL1_IO_9 R9 LVTTL1_IO_10 T10 D7 E7 LVTTL1_IO_11 U12 Reserved LATCH 0 U11 G7 H7 Reserved LATCH 1 P12 Reserved SYNC 0 R12 B8 C8 Reserved SYNC 1 AB11 LVTTL1_IO_12 AB10 E8 F8 LVTTL1_IO_13 AA12 LVTTL1_IO_14 W9 H8 I8 LVTTL1_IO_15 AB5 Signal Positions GND C1 F1 I1 L1 A2 D2 G2 J2 C3 F3 I3 L3 A4 D4 G4 J4 C5 F5 I5 L5 A6 D6 G6 J6 C7 F7 I7 L7 A8 D...

Страница 26: ...rdware Manual Doc Nr E 1108 21 Rev 1 0 ECS CPCIs FPGA See Figure 7 PCB top view of ECS CPCIs FPGA on page 15 for the position of the pins Pin Signal Direction 1 3V3 2 TDI Input 3 TDO Output 4 TCK Input 5 TMS Input 6 GND 5 3 JTAG FPGA X1300 ...

Страница 27: ...Declaration of Conformity ECS CPCIs FPGA Hardware Manual Doc Nr E 1108 21 1 0 Page 27 of 28 6 Declaration of Conformity ...

Страница 28: ...act our sales team Table 14 Order information hardware PDF Manuals For the availability of the manuals see table below Please download the manuals as PDF documents from our esd website https www esd eu for free Manuals Order No ECS CPCIs FPGA ME Hardware manual in English E 1108 21 EtherCAT Slave Stack ME EtherCAT Slave Stack manual in English P 4520 21 Table 15 Available manuals Printed Manuals I...

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