Epson S1C6200, Руководство центрального процессора

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Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
S1C6200/6200A CORE CPU MANUAL
EPSON
65
3 INSTRUCTION SET
POP XL
Pop stack data into XL
POP XL
XL
←
M(SP), SP
←
SP + 1
1 1 1 1 1 1 0 1 0 1 1 0 FD6H
VI
5
Not affected
Not affected
Not affected
Not affected
Loads the contents of the data memory location addressed by the stack pointer
into XL, the four low-order bits of X. SP is incremented by 1.
POP XL
SP C0 C1
Memory (C0H) 0001 0001
XL register 1101 0001
POP XP
Pop stack data into XP
POP XP
XP
←
M(SP), SP
←
SP + 1
1 1 1 1 1 1 0 1 0 1 0 0 FD4H
VI
5
Not affected
Not affected
Not affected
Not affected
Loads the contents of the data memory location addressed by the stack pointer
into XP, the 4-bit page part of IX. SP is incremented by 1.
POP XP
SP B4 B5
Memory (B4H) 0101 0101
XP register 0111 0101
2 3 2 2 2 1 2 0
M(SP) =
= XP
2 0
2
1
2
2
2 3
2 3 2 2 2 1 2 0
M(SP) =
= XL
2 0
2
1
2
2
2 3