Endace Measurement Systems Limited
http://www.endace.com
EDM01.05-04r1 DAG 3.6GE User Manual
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2
Revision 7. 22 September 2005.
1.2 DAG 3.6GE Card Product Description
The DAG Ethernet port will operate in half duplex or full duplex modes.
The DAG 3.6GE card by default finds the fastest link configuration
possible with the peer device using Ethernet Autonegotiation.
Figure
Figure 1-1 shows the DAG 3.6GE series PCI card.
Figure 1-1. DAG 3.6GE series PCI Card.
1.3 DAG 3.6GE Card Architecture
Description
The DAG 3.6GE PCI-bus card is designed for cell and packet capture and
generation on IP networks.
Serial Ethernet data is received by the interface, and fed through a framer
into the first of the two Xilinx FPGAs.
This FPGA contains an Ethernet processor and the DUCK timestamp
engine.
Because of component close association, packets or cells are time-stamped
accurately. Time stamped packet records are stored in the second FPGA,
which interfaces to the PCI bus. All packet records are written to host PC
memory during capture operations.
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