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Supported mainframe features 231
Mainframe Features and Support
the appropriate level of DFSMS, and the Enginuity revision
supporting this feature.
Multiple Allegiance
(MA) The Symmetrix DMX systems support Multiple Allegiance (MA), an
IBM feature that improves throughput across a shared storage
environment. MA allows different hosts to concurrently access the
same device (have concurrent implicit allegiances), as long as I/Os do
not conflict with each other.
The Symmetrix DMX systems support MA as a 2105 or 2107 control
unit if the COM-PAV feature is enabled on the Symmetrix system.
The Symmetrix system can also support MA when the Symmetrix
system is defined to the host as a 3990-6 by enabling this feature on
the Symmetrix service processor.
Parallel Access
Volumes The Symmetrix DMX systems support Parallel Access Volumes, an
IBM feature that improves response time by reducing device
contention, resulting in higher performance and throughput. To
enable this capability, users also must license the COMPAV/MA
feature from EMC. The Symmetrix DMX systems must be defined to
the host as a 2105 or 2107 control unit to support Parallel Access
Volumes.
“Compatible HyperPAV” in the following section contains
additional information.
Compatible
HyperPAV Compatible HyperPAV offers enhancements to Parallel Access
Volumes (PAV) designed to achieve equal or better performance than
possible with the original PAV feature alone while also using the
same or fewer z/OS resources. HyperPAV allows an alias address to
be used to access any base on the same control unit image per I/O
base. This capability also allows different HyperPAV hosts to use one
alias to access different bases, which reduces the number of alias
addresses required to support a set of bases in z/OS environment
with no latency in targeting an alias to a base.
Support for HyperPAV is a separately licensed feature and has a
prerequisite of Compatible PAVs which is also a separately licensed
product.
Dynamic Parallel
Access Volumes Parallel Access Volumes/Multiple Allegiance (PAV/MA) is a
mainframe-exclusive feature that resolves the z/OS limitation
allowing only one outstanding I/O operation to a device (
Figure 51
on page 232 ). The PAV/MA feature was introduced with the IBM ESS