CPU & PCI Bus Control
Scroll to this item and press <Enter> to view the following screen:
CMOS Setup Utility – Copyright (C) 1984 – 2001 Award Software
CPU & PCI Bridge Control
Item Help
PCI1 Master 0 WS Write
[Enabled]
PCI2 Master 0 WS Write
[Enabled]
PCI1 Post Write
[Enabled]
PCI2 Post Write
[Enabled]
PCI Delay Transaction
[Disabled]
Menu Level
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+/-/PU/PD:Value:
F10: Save ESC: Exit F1:General Help
F5:Previous
Values
F6:Fail-Safe
Defaults F7:Optimized
Defaults
PCI 1/2 Master 0 WS Write (Enabled)
When enabled, writes to the PCI bus are executed with zero wait states, pro-
viding faster data transfer.
PCI 1/2 Post Write (Enabled)
When enabled, writes from the CPU to PCU bus are buffered, to compensate
for the speed differences between the CPU and PCI bus. When disabled, the
writes are not buffered and the CPU must wait until the write is complete be-
fore starting another write cycle.
PCI Delay Transaction (Disabled)
The mainboard’s chipset has an embedded 32-bit post write buffer to support
delay transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1.
Press <Esc> to return to the Advanced Chipset Setup screen.
Memory Hole (Disabled)
This item is used to reserve memory space for ISA expansion cards that re-
quire it.
System BIOS/Video RAM Cacheable (Disabled)
These items allow the video and system to be cached in memory for faster
execution. Leave these items at the default value for better performance.
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