Elgo FMAX2 Series, Руководство по эксплуатации

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SSI Interface
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8 SSI Interface
8.1 SSI - Functional Principle
If the clock is not interrupted for the time Tm-T/2 (output of further 25 periods), the shift register clocks once
again the same data value (error recognition in evaluation).
With the SSI interface, transmission rates up to max. 250 KHz can be ensured.
Figure 10: Read SSI data
Two different codings are possible for the SSI:

Order option SB0 with 25 bit binary code

Order option SG0 with 25 bit Gray code
Details see Type Designation

12.1
9 Optional Incremental Outputs
9.1 Incremental A/B Signals (TTL / HTL)
Optionally two 90° phase shifted, rotary pulse encoder compatible square-wave signal outputs with HTL or TTL
level (push/pull) are available. Order specifications see

12.1.
Figure 11: Incremental A/B signals (TTL / HTL)
T
Tm-T/2
1 1 G24 G23 G22 G21 G20 G19 G18 G17 G16 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 0 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Non-inverted SSI clock
24 bit
T = Period time of the clock signall
TM = Monoflop time >15 µs
B
A
90°
HTL: 10 … 30 V
TTL : 5 V
0 V