Elan Digital Systems Ltd.
15
AD125 USER’S GUIDE
To decrement the WRITE POINTER by TWO, do a write access to
the DECW port with don’t care data. Remember that in FIFO mode,
you may get an IREQ when changing the WRITE POINTER
through a half or quarter count (just as you would if the AD125
passed these points whilst running at full speed...use the SELCTRD
bit to block interrupts whilst manipulating the WRITE POINTER if
this is a problem...see section on interrupts).
To clear all system counters to 7FFFh do the following:
1.
Write access to CLRCT port with don’t care data. This will clear
the bottom 8-bits ONLY (it will also pre-load the MUXSEQ
counter...see section on INPUT MUX CONTROL)
2.
With software, remember the value of the BUFFLEN byte (note
that the CTLEN port is WRITE ONLY), write to the CTLEN port
with 00h, then with BUFFLEN byte. This will clear the upper 7-
bits of the counters.
3.
If in FIFO mode: pulse the SELCTRD bit in SETUP REG 2 to 0-
1-0 to clear the possible artificial IREQ event caused by the
internal counter outputs changing state.
The READ and WRITE POINTERS can be read via port 4 and 5
(low byte high byte respectively). Bit 6 of SETUP REG 2 controls
whether the READ or WRITE pointer is readable: 0
→
READ
POINTER, 1
→
WRITE POINTER. Do not read either pointer
while the AD125 is running or samples will be stored in the wrong
order in SRAM. Note that this bit is dual purpose and also serves to
clear IREQ events (without having to read the SRAM).
3.3.3 PRE-TRIGGER DEPTH
Before performing a BURST acquisition the WRITE POINTER
must be pre-decremented at least once by software (i.e. 2 bytes).
This will give a pre-trigger depth of 1 conversion. To make the pre-
trigger depth greater simply pre-decrement the WRITE POINTER
extra times, each write to the DECW port will give one conversion
more pre-trigger. So to set 200 conversions for the pre-trigger
depth, pre-clear the pointers (3.3.2) and then write 200 times to the
DECW port (don’t care data).