User Guide • PC3-ALLEGRO • CompactPCI
®
PlusIO CPU Board • Intel® i7-3xxx Processor
Read/Clear Status Register 0
Write: SMBus Address 0xB0
Read: SMBus Address 0xB1
Bit
Description CMD_STAT0
7
PF18S
0=Normal operation
1=Last system reset may be caused by a power failure of the +V1.8S voltage regulator
6
PF15S
0=Normal operation
1=Last system reset may be caused by a power failure of the +V1.5S voltage regulator
5
RESERVED
Always read as 0
4
PFVSA
0=Normal operation
1=Last system reset may be caused by a power failure of the CPU +VCC_SA voltage regulator
3
PF105L
0=Normal operation
1=Last system reset may be caused by a power failure of the +V1.05LAN voltage regulator
2
PF105S
0=Normal operation
1=Last system reset may be caused by a power failure of the +V1.05S voltage regulator
1
PFVRG
0=Normal operation
1=Last system reset may be caused by a power failure of the CPU +VCC_AXG voltage regulator
0
PFVRC
0=Normal operation
1=Last system reset may be caused by a power failure of the CPU +VCC_CPU voltage regulator
The bits in this register are sticky, i.e. their state will be kept even if a system reset occurs. To clear the
bits a write to the register with arbitrary data may be performed.
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