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Datasheet of TDGL004 - BOARD CEREBOT 32MX7 PIC32MX795
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Cerebot 32MX7 Reference Manual
www.digilentinc.com
page 9 of 19
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The four LEDs are connected to bits 12-15 of
PORTG. LED 1 is connected to bit 12, LED 2
is connected to bit 13, and so on. To use the
LEDs, set the desired bits as outputs by
clearing the corresponding bits in the TRISG
register and set the bits to the desired value in
the PORTG register. Setting a bit to 1 will
illuminate the LED and setting the bit to 0 will
turn it off.
CPU Clock Source
The PIC32 microcontroller supports numerous
clock source options for the main processor
operating clock. The Cerebot 32MX7 board is
designed to support either a silicon resonator
from Discera, IC2, for use with the EC
oscillator option, or an external crystal for use
with the XT oscillator option. Standard
production boards will have an 8Mhz Discera
silicon resonator loaded and the EC oscillator
option should be used. If IC2 is not loaded, an
8Mhz crystal will be loaded for X1 (on the
bottom of the board) and the XT oscillator
option should be used. Oscillator options are
selected via the configuration settings specified
using the #pragma config statement. Use
#pragma config POSCMOD=EC
to select the
EC option and
#pragma config POSCMOD=XT
to select the XT option.
Using the internal system clock phase-locked
loop (PLL), it is possible to select numerous
multiples or divisions of the 8Mhz oscillator to
produce CPU operating frequencies up to
80Mhz. The clock circuit PLL provides an input
divider, multiplier, and output divider. The
external clock frequency (8Mhz) is first divided
by the input divider value selected. This is
multiplied by the selected multiplier value and
then finally divided by the selected output
divider. The result is the system clock,
SYSCLK, frequency. The SYSCLK frequency
is used by the CPU, DMA controller, interrupt
controller and pre-fetch cache.
The operating frequency is selected using the
PIC32MX795 configuration variables. These
are set using the
#pragma config
statement.
Use
#pragma config FPLLIDIV
to set the
input divider,
#pragma config FPLLMUL
to set
the multiplication factor and
#pragma config
FPLLODIV
to set the output divider. Refer to the
PIC32MX5XX/6XX/7XX Family Data Sheet
and the PIC32MX Family Reference Manual,
Section 6. Oscillators for information on how to
choose the correct values, as not all
combinations of multiplication and division
factors will work.
In addition to configuring the SYSCLK
frequency, the peripheral bus clock, PBCLK,
frequency is also configurable. The peripheral
bus clock is used for most peripheral devices,
and in particular is the clock used by the
timers, and serial controllers (UART, SPI, I2C).
The PBLCK frequency is a division of the
SYSCLK frequency selected using
#pragma
config FPBDIV
. The PBCLK divider can be
set to divide by 1, 2, 4, or 8.
The following example will set up the Cerebot
32MX7 for operation with a SYSCLK frequency
of 80Mhz and a PBCLK frequency of 10Mhz:
#pragma config FNOSC = PRIPLL
#pragma config POSCMOD = EC
#pragma config FPLLIDIV = DIV_2
#pragma config FPLLMUL = MUL_20
#pragma config FPLLODIV = DIV_1
#pragma config FPBDIV = DIV_8
10 / 20
10 / 20