ECS X77H2-A3, Руководство пользователя, Страница: 53 / 76

Chapter 3
X77H2-A3 USER MANUAL
49
Chipset OverClocking Configuration
Scroll to this item to view the following screen:
The selection of Perfor-
mance Memory Profiles
which impacts memory siz-
ing behavior.
Main Advanced Chipset M.I.B III Boot Security Save & Exit
+/- : Change Opt.
Enter/Dbl Click : Select
lk
mn
: Select Screen
/Click: Select Item
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save & Exit
ESC/Right Click: Exit
Row Precharge Time (tRP) (9)
This item specifies Row precharge to Active or Auto-Refresh of the same bank.
Memory Timing Configuration
This item shows the information of Memory Timing.
CAS Latency (tCL) (9)
This item determines the operation of DDR SDRAM memory CAS (colulmn address
strobe). It is recommended that you leave this item at the default value. The 2T
setting requires faster memory that specifically supports this mode.
Memory Multiplier Configuration
This item shows the information of Memory multiplier Configuration.
RAS# to CAS# Delay (tRCD) (9)
This item specifies the RAS# to CAS# delay to Rd/Wr command to the same bank.
Row Refresh Cycle Time (tRFC) (128)
This item specifies the row refresh cycle time.
Memory Multiplier Configuration
Performance Memory Profiles Automatic
Memory Timing Configuration
CAS# Latency (tCL) : 9
RAS# to CAS# Delay (tRCD) 9
Row Precharge Time (tRP) 9
RAS# Active Time (tRAS) 28
Write Recovery Time (tWR) 12
Row Refresh Cycle Time (tRFC) 128
Active to Active Delay (tRRD) 5
Write to Read Delay (tWTR) 6
Read CAS# Precharge (tRTP) 6
Four Active Window Delay (tFAW) 24
Intel Graphics Configuration
Graphics Core Ratio Limit 13
Graphics Voltage (1/256 V) 0
RAS# Active Time (tRAS) (28)
This item specifies the RAS# active time.
Write Recovery Time (tWR) (12)
This item specifies the write recovery time.
Active to Active Delay (tRRDmin) (5)
This item controls the ACTIVE bank x to ACTIVE bank y in memory clock cycles.