CPU & PCI Bus Control
Scroll to this item and press <Enter> to view the following screen:
Phoenix – AwardBIOS CMOS Setup Utility
CPU & PCI Bridge Control
Item Help
CPU to PCI Write Buffer
[Enabled]
PCI Master 0 WS Write
[Enabled]
PCI Delay Transaction
[Enabled]
Menu Level
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+/-/PU/PD:Value:
F10: Save ESC: Exit F1:General Help
F5:Previous Values
F6:Fail-Safe Defaults
F7:Optimized Defaults
CPU to PCI Write Buffer (Enabled)
When enabled, writes from the CPU to PCU bus are buffered, to compensate
for the speed differences between the CPU and PCI bus. When disabled, the
writes are not buffered and the CPU must wait until the write is complete be-
fore starting another write cycle.
PCI Master 0 WS Write (Enabled)
When enabled, writes to the PCI bus are executed with zero wait states.
PCI Delay Transaction (Enabled)
The mainboard’s chipset has an embedded 32-bit post write buffer to support
delay transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1.
Memory Hole (Disabled)
This item is used to reserve memory space for ISA expansion cards that re-
quire it.
System BIOS/Video RAM Cacheable (Disabled)
These items allow the video and system to be cached in memory for faster
execution. Leave these items at the default value for better performance.
Press <Esc> to return to the Advanced Chipset Features screen.
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