ECS 651C-M, Руководство пользователя

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Using BIOS
AGP Aperture Size(128MB)
This setting controls just how much system RAM can be allocated to AGP for video
purposes. The aperture is a portion of the PCI memory address range dedicated to graphics
memory address space. Host cycles that hit the aperture range are forwarded to the AGP
without any translation.
Graphic Window WR Combin (Disabled)
Use this item to enable or disable CPU support for WR Combin feature.
AGP Fast Write Support (Enabled)
This item lets you enable or disable the caching of display data for the video memory
of the processor.
AGP Data Rate (Auto)
This item allows users to set the AGP Data Rate by, Auto, 1X, 2X, 4X, or 8X,
depending on what speed the AGP card supports.
AGP & P2P Bridge Control (Press Enter)
Scroll to this item and press <Enter> to view the following screen:
AGP Aperture Size [128M]
Graphic Windows WR Combin [Disabled]
AGP Fast Write Support [Enabled]
AGP Data Rate [Auto]
Phoenix-AwardBIOS CMOS Setup Utility
AGP & P2P Bridge Control
Item Help
Menu Level
: Move Enter: Select +/-/PU/PD:Value F10:Save ESC:Exit F1: General Help
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
• DRAM CAS Latency (2.5T) : This item controls the timing delay (in clock
cycles) before the DRAM starts a read command after receiving it.
• RAS Active Time (tRAS) (6T) : This item allows you to set the amount of time
a RAS can be kept open for multiple accesses. High figures will improve
performance.
• RAS Precharge Time (tRP) (3T) This is the duration of the time interval
during which the Row Address Strobe signal to a DRAM is held low during
normal Read and Write Cycles. This is the munimum interval between com-
pleting one read or write and starting another from the same (non-page mode)
DRAM. Techniques such as memory interleaving, or use of Page Mode DRAM
are often used to avoid this delay. Some chipsets require this parameter in
order to set up the memory configuration properly. The RAS Precharge value
is typically about the same as the RAM Access (data read/write) time.
• RAS to CAS Delay (tRCD) (3T) : This is the amount of time a CAS is per-
formed after a RAS. This lower the better, but some DRAM does not support
low figures.
Press <Esc> to return to the Advanced Chipset Features page.
Press <Esc> to return to the Advanced Chipset Features screen.