Embedded Solutions
Page 13 of 50
machine will load the start address, send the opening flag character and begin sending
data sequentially LSB first until the end address is reached and the closing flag is sent.
If the TX clear is enabled, the transmitter will be automatically disabled when the
transmission is complete. Otherwise, the transmitter will wait, pointing at the next
address after the end address. If additional data has been or is later written to the
DPR, a new message can be started by entering a new end address. The transmit
state-machine will then start a new message and continue sending data until the new
end address has been reached. If the end of the second DPR block is reached before
the end address, the transmitter will proceed to the beginning of the first DPR block and
continue until the end address is reached. Likewise when the end of the first DPR is
reached, the transmitter continues with the beginning of the second DPR.
To receive a message the receiver must be enabled, but only the starting address of
the receive buffer needs to be specified. Data will be stored sequentially starting at that
address until the closing flag is detected. This will latch an RX interrupt status and can
cause an interrupt if enabled. The last address that data (16-bit words) is stored in is
latched and can be read from the control register as a read-only field.
The transmit interrupt is mapped to the first interrupt line of the channel block and the
receive interrupt is mapped to the second interrupt line. The remaining two interrupt
lines are not used in SDLC mode.
An asynchronous interface is also available on the PMC BiSerial-III-HW2. This protocol
uses one start-bit (low) eight data-bits no parity and one stop-bit (high). The marking
(idle) state of the line is high and eleven bit-periods of this high state will be interpreted
as the end-of-message condition.
The clock reference is supplied by either PLL clock B or 5 MHz derived from the on-
board oscillator. This frequency is sixteen times the bit rate of the interface. The
transmit clock is derived by a straight divide-by sixteen circuit, while the receive state-
machine uses the higher frequency to detect data bits and will re-sync its clock counter
when detected data transitions are close but not exactly on sixteen clock boundaries.
This allows for greater flexibility in matching transmitter and receiver clock frequencies.
Each asynchronous interface uses two DPR blocks, one for the transmitter and one for
the receiver. The process of sending and receiving messages is similar to the SDLC
interface except that only half as much memory is available for the receive and transmit
buffers. Also the receiver end address that is latched when a received message
completes is a byte address. That is the lower two bits of the address specify which
byte was the last to be written, while the remaining address bits specify the 32-bit word
that contains that byte e.g. an end address of 0x3ff would indicate that all four bytes of
the 255
th
word of the receive DPR were written.
The transmit interrupt is mapped to the first or third interrupt line of the channel block
and the receive interrupt is mapped to the second or fourth interrupt line.
