Dolby Laboratories Lake LP4D12, Руководство пользователя

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Dolby
®
Lake
®
Processor System Manual Connecting Digital Audio Devices
48
192 kHz sample rates. The user can configure the Processor to provide a different
sample rate for each stereo digital channel.
Figure 7-1 shows a simplified block diagram of the Processor clock system.
BNC
AES1
AES2
AES3
AES4
SPDIF
48 kHz
INTERNAL
PRIMARY
CLOCK
48 kHz
96 kHz
192 kHz
BNC
AES1
AES2
AES3
AES4
SPDIF
48 kHz
INTERNAL
SAMPLE RATE
CONVERTER
CLOCK
48 kHz
96 kHz
192 kHz
44.1 kHz
88.2 kHz
176.4 kHz
44.1 kHz
INTERNAL
AES1
AES2
AES3
AES4
SPDIF
AES5
AES6
AES7
AES8
INPUTS OUTPUTS
AUTO/
MANUAL 48
AUTO/
MANUAL 44
c
c
c
c
c
c
c
c
c
c
c
c
c
Figure 7-1 Dolby Lake Processor Clock System
In Figure 7-1, each circled C represents a choice point. A choice point is a user-
interface control that can be configured using the Dolby Lake Controller software.
For further information on the software user interface, please refer to the
Dolby Lake
Controller Manual .
Both the Primary and Sample Rate Converter clocks can either derive their own
internal clock signal, or synchronize to an external input clock source. The available
input clock sources, shown in Figure 7-1, are BNC word clock input, AES pair 1,
AES pair 2, AES pair 3, AES pair 4, and S/PDIF. The end user can choose which
input clock source is desired.