DLP Design USB-Parallel FIFO Module DLP-USB245R, Руководство пользователя, Страница: 4 / 13

Rev. 1.0 (November 2008) 4 © DLP Design, Inc.
2.0 TIMING DIAGRAMS
T
T
I
I
M
M
E
E
D
D
E
E
S
S
C
C
R
R
I
I
P
P
T
T
I
I
O
O
N
N
M
M
I
I
N
N
M
M
A
A
X
X
U
U
N
N
I
I
T
T
T1 RD# Active Pulse Width 50 - nS
T2 RD# to RD# Pre-Charge Time 50 + T6 - nS
T3 RD# Active to Valid Data* 20 50 nS
T4 Valid Data Hold Time from RD# Inactive* 0 - nS
T5 RD# Inactive to RXF# 0 25 nS
T6 RXF# Inactive After RD Cycle 80 - nS
*Load = 30pF
T
T
I
I
M
M
E
E
D
D
E
E
S
S
C
C
R
R
I
I
P
P
T
T
I
I
O
O
N
N
M
M
I
I
N
N
M
M
A
A
X
X
U
U
N
N
I
I
T
T
T7 WR Active Pulse Width 50 - nS
T8 WR to WR Pre-Charge Time 50 - nS
T9 Valid Data Setup to WR Falling Edge* 20 - nS
T10 Valid Data Hold Time from WR Inactive* 0 - nS
T11 WR Inactive to TXE# 5 25 nS
T12 TXE# Inactive After WR Cycle 80 - nS
*Load = 30pF
T6
T5
RXF#
T1 T2
RD#
T3 T4
D
Description Min Max Unit
Valid data
D[7 ..0]
Valid data D[7 ..0]
T 10
T 9
TXE#
WR
T11
T12
T7
T8