3. VC-20™ Connector Signals for Serial Speech Data Interface
SCLK
The Serial port shift clock clocks in both the received speech data and the transmitted speech
data. The frequency of this signal must be within the range 128kHz. – 5.16MHz.. Data is
clocked out on the rising edge of SCLK and clocked in on the falling edge (see Section 6.
Timing Diagrams).
DX
The speech data from the VC-20™ is clocked serially out on DX. These 16-bit linear words are
clocked out MSB first. The range of these twos complement coded words is –32768 to 32767.
(see Section 6. Timing Diagrams).
DR
The Speech data to the VC-20™ is clocked in serially on DR. These 16-bit linear words are
clocked in MSB first. The range of these twos complement coded words is –32768 to 32767.
(see Section 6. Timing Diagrams). It is recommended that the speech input be zero-mean at an
average level of 22dbm0. Note: The maximum sinusoidal input (+/-32767) corresponds to +3.17
dBm0.
FSR, FSX
The data input and output framing signals must come at a frequency of 8kHz. and have a
duration of one cycle of SCLK. These two signals must come from the same source (see Section
5. Example Configuration). As outlined below FSX must be tri-stated when SP_RDY is low to
avoid multiple drivers on the same line.
SP_RDY
This active High Signal indicates that the serial port is ready to deliver and receive speech data.
SP_RDY is low upon reset, once it goes high it stays high until another reset condition occurs.
When SP_RDY is low FSX must be tri-stated to avoid a double driving condition. To avoid a
reboot, the 8kHz. framing signals must be valid once SP_RDY becomes active (see figure
below). The speech input data is ignored for a period of 10-50ms. after activation of SP_RDY
while initialization of the channel occurs. (see Section 5. Example Configuration)
SP_RDY
FSX
FSR
(Don’t Care)
(Tri-stated)
