DIGITAL-LOGIC AG
MSMX104 Manual V1.3
13
SD[O..15], input/output
These signals provide bus bits 0 through 15 for the microprocessor, memory, and I/0 devices. DO is the
least-significant Bit and D15 is the most significant Bit. All 8-Bit devices on the I/O channel should use DO
through D7 for communications to the microprocessor. The 16-Bit devices will use DO through D15. To
support 8-Bit device, the data on D8 through D15 will be gated to DO through D7 during 8-Bit transfers to
these devices; 16-Bit microprocessor transfers to 8-Bit devices will be converted to two 8-Bit transfers.
/SMEMR input/output
These signals instruct the memory devices to drive data onto the data bus for the first MByte. /SMEMR is
active on all memory read cycles. /SMEMR may be driven by any microprocessor or DMA controller in the
system. When a microprocessor on the I/0 channel wishes to drive /SMEMR, it must have the address
lines valid on the bus for one system clock period before driving /SMEMR active. The signal is
active low
.
/SMEMW, input/output
These signals instruct the memory devices to store the data present on the data bus for the first MByte.
/SMEMW is active in all memory read cycles. /SMEMW may be driven by any microprocessor or DMA
controller in the system. When a microprocessor on the I/O channel wishes to drive /SMEMW, it must
have the address lines valid on the bus for one system clock period before driving /SMEMW active. Both
signals are
active low.
SYSCLK, output
This is a 8 MHz system clock. It is a synchronous microprocessor cycle clock with a cycle time of 167
nanoseconds. The clock has a 66% duty cycle. This signal should only be used for synchronization.
TC output
Terminal Count provides a pulse when the terminal count for any DMA channel is reached. The TC
completes a DMA-Transfer. This signal is expected by the onboard floppy disk controller. Do not use this
signal, because it is internally connected to the floppy controller.
/OWS, input
The Zero Wait State (/OWS) signal tells the microprocessor that it can complete the present bus cycle
without inserting any additional wait cycles. In order to run a memory cycle to a 16-Bit device without wait
cycles, /OWS is derived from an address decode gated with a Read or Write command. In order to run a
memory cycle to an 8-Bit device with a minimum of one-wait states, /OWS should be driven active one
system clock after the Read or Write command is active, gated with the address decode for the device.
Memory Read and Write commands to an 8-Bit device are active on the falling edge of the system clock.
/OWS is
active low
and should be driven with an open collector or tri-state driver capable of sinking
2OmA.
12V
+/- 5%
not used.
GROUND = 0V
used for the entire system.
VCC, +5V +/- 0.25V
for logic supply.
