Nexys4 DDR™ FPGA Board Reference Manual
Copyright Digilent, Inc. All rights reserved.
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15.2 Microphone Digital Interface Timing
The clock input of the microphone can range from 1 MHz to 3.3 MHz based on the sampling rate and data
precision requirement of the applications. The L/R Select signal must be set to a valid level, depending on which
edge of the clock the data bit will be read. A low level on L/RSEL makes data available on the rising edge of the
clock, while a high level corresponds to the falling edge of the clock, as shown in Figure 27.
Pulse
Pulse
Pulse
Pulse
CLK
DATA1
DATA2
< 20 ns
> 30 ns
> 30 ns
< 20 ns
Figure 27. PDM Timing Diagram.
The typical value of the clock frequency is 2.4 MHz. Assuming that the application requires 7-bit precision and 24
KHz, there can be two counters that count 128 samples at 12 KHz, as shown in Figure 28.
128 Samples
53.3ns
128 Samples
128 Samples
Counter 1 Counting
Counter 1
Counting
Counter 2 Counting
41.6ns
0.416ns
83.2ns
Clock
Data
0 1 ... 0 1 1
0 1 1
0 1 1
0 1 1
...
...
...
Figure 28. Sampling PDM with two counters.
16 Mono Audio Output
The on-board audio jack (J8) is driven by a Sallen-Key Butterworth Low-pass 4
th
Order Filter that provides mono
audio output. The circuit of the low-pass filter is shown in Figure 29. The input of the filter (AUD_PWM) is
connected to the FPGA pin A11. A digital input will typically be a pulse-width modulated (PWM) or pulse density
modulated (PDM) open-drain signal produced by the FPGA. The signal needs to be driven low for logic ‘0’ and left
in high-impedance for logic ‘1’. An on-board pull-up resistor to a clean analog 3.3V rail will establish the proper
voltage for logic ‘1’. The low-pass filter on the input will act as a reconstruction filter to convert the pulse-width
modulated digital signal into an analog voltage on the audio jack output.
