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NetFPGA-SUME™ Reference Manual

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When the input voltage falls below 9 volts, or the power switch transitions to the "OFF" position, the LTC2974s
perform a time-based off sequence and the rails come down in the following order:

1.

MGTVAUX

2.

VCC1V5, QDRVTT, and DDRVTT

3.

VCC3V3

4.

MGTAVTT

5.

MGTAVCC

6.

VCC2V0

7.

VCC1V8

8.

VCC1V0

Figure 8. Power ON/OFF sequence.

The LTC2974s constantly monitor the output voltage, current, and temperature associated with each channel
(supply rail). This information, referred to as telemetry data, is used to determine the on status of each supply rail,
as well as monitor for fault and warning conditions. When a fault or a warning occurs, the FPGA application may be
notified via an interrupt that is signaled by the LTC2974's ALERTB, AUXFAULTB, or FAULTB1 pins. The FPGA
application may then read (using I2C) one or more of the LTC2974 status registers (defined in the datasheet) to
determine the source of the fault or the warning. The output voltage, current, power, and temperature associated
with any channel may also be read using the applicable PMBUS (I2C) commands, which are defined in the LTC2974
datasheet.

In order to generate faults and warnings, each channel of the LTC2974 must be configured with a nominal output
voltage, under voltage warning limit, over voltage fault limit, under current warning limit, over current warning
limit, over current fault limit, under current fault limit, under temperature warning limit, under temperature fault
limit, and over temperature fault limit. Tables 2 and 3 describe the voltage and current limits as pre-configured by
Digilent during the manufacturing process.

Supply
Rail

Under Voltage
Fault Limit

Under Voltage
Warning Limit

Nominal
Voltage

Overvoltage
Warning Limit

Overvoltage Fault
Limit

VCC1V0

0.9V

0.925V

1.0V

1.075V

1.1V

VCC1V8

1.62V

1.665V

1.8V

1.935V

1.98V

VCC2V0

1.8V

1.85V

2.0V

2.15V

2.2V

MGTAVCC

0.9V

0.925V

1.0V

1.075V

1.1V

MGTAVTT

1.08V

1.11V

1.2V

1.29V

1.32V

VCC3V3

2.97V

3.0525V

3.3V

3.5475V

3.63V

VCC1V5

1.35V

1.3875V

1.5V

1.6125V

1.65V

MGTVAUX

1.62V

1.665V

1.8V

1.935V

1.98V

DDRVTT

N/A

N/A

0.75V

N/A

N/A

QDRVTT

N/A

N/A

0.75V

N/A

N/A

Table 2. Voltage fault and warning limits.

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Содержание NetFPGA-SUME

Страница 1: ...y Two 4GB DDR3 SODIMMs MT8KTF51264Hz 1G9E1 64 bit wide buses clocked at 850 MHz 1700 mbps Three 72Mbit QDRII SRAMs CY7C25652KV18 500BZXC 36 bit wide buses clocked at 500 MHz 1000 mbps Storage Two SATA III ports 6 gbps via GTH transceivers Micro SD Card Slot Two 512Mbit Micron StrataFlash parallel flash modules PC28F512G18A For bitfile storage only Communication Interfaces PCI E Gen3 x8 supporting ...

Страница 2: ... as well as the ISE toolset which includes ChipScope and EDK The Virtex 7 XC7V690T FPGA is not a WebPack device which means full licenses will need to be acquired for these tools in order to build designs that target the NetFPGA SUME Licensing information for Vivado can be found here Academic institutes can make a request to the Xilinx University Program for a donation of full Vivado licenses here...

Страница 3: ...ion For more information on the NetFPGA organization go here 2 Power 2 1 Input Supply The NetFPGA SUME receives power via a 2 x 4 pin PCI Express Auxiliary Power Connector The 2x4 pin PCI Express Auxiliary Power receptacle header J14 can accept both 2x3 and 2x4 pin PCI Express Auxiliary Power Plugs found on a standard ATX power supply When installed on a PC motherboard you can plug the 2x3 or 2x4 ...

Страница 4: ...connector J14 Figure 4 describes pin out of the power connector header J14 when a 2x4 pin or a 2x3 pin plug is used The Sense0 and Sense1 pins are to be connected to GND when power is present and left floating otherwise Since the 2x3 pin plug does not include a Sense1 pin it s possible to determine what type of plug is present and thus how much power can be consumed The FPGA logic can determine wh...

Страница 5: ... and QDRII I O supplies are powered from the VCC1V5 rail two ferrite beads are also included to prevent high speed switching noise caused by one memory from affecting the other Figure 6 shows how the various supplies are derived from the input A Linear Technology LTC6909 is used to generate six out of phase 302 KHz clocks Each clock is 60 degrees out of phase with any of the other clock outputs se...

Страница 6: ...pervising The components on the NetFPGA SUME require that the supply voltages be sequenced on and off in a particular order The NetFPGA SUME utilizes two Linear Technology LTC2974s to ensure that these sequencing requirements are met Each LTC2974 supports cascade sequence ON with time based sequence off and can monitor the input voltage four output voltages four output currents and four external t...

Страница 7: ...ages Figure 7 LTC2974 sequencer and supervisor Figure 7 depicts the connections between the two LTC2974s as well as the signals that are used to control the power on and off sequence When the input voltage VCC12V0 exceeds 10 volts the LTC2974s will perform a power on sequence when the power switch SW1 is placed in the ON position When a power on sequence is performed the rails come up in the follo...

Страница 8: ... the source of the fault or the warning The output voltage current power and temperature associated with any channel may also be read using the applicable PMBUS I2C commands which are defined in the LTC2974 datasheet In order to generate faults and warnings each channel of the LTC2974 must be configured with a nominal output voltage under voltage warning limit over voltage fault limit under curren...

Страница 9: ...errupt by driving the ALERTB AUXFAULTB or FAULTB1 pins The ALERTB pin of the LTC2974 is an open drain output that is driven low whenever a fault or warning occurs The ALERTB pins of the two LTC2974s IC43 and IC44 are connected in a wire and fashion via the PCON_ALERT_B net to pin J41 of the FPGA IC12 as shown in Fig 9 Enabling the internal pull up on pin J41 will allow the FPGA application to use ...

Страница 10: ...tect when one of the faults described above has occurred Figure 10 AUXFUALTB interrupt source The FAULTB1 pin of the LTC2974 is bi directional open drain input output that can be configured to drive low in response to any channel entering a faulted off state The LTC2974 can also be configured to disable any given channel in response to a logic low being detected on the FAULTB1 pin However it has b...

Страница 11: ...ng 100 efficient The switching regulators used on the NetFPGA SUME were designed to operate at approximately 90 efficiency The total power consumed from the input supply can be as high as 40 22 5 47 4 49 5 8 3 6 0 90 12 0 6 184 4 Watts However this number can be a bit misleading as it assumes that a mezzanine module is attached to the FMC connector and is drawing the maximum allowable current from...

Страница 12: ...Bitstreams are stored in SRAM based memory cells within the FPGA This data defines the FPGA s logic functions and circuit connections and it remains valid until it is erased by removing board power by pressing the reset button attached to the PROG input by writing a new configuration file using the JTAG port or by triggering the onboard CPLD to load a new bitstream from the parallel flash A Virtex...

Страница 13: ...he firmware for the CPLD so that four different bitstreams can be stored in the flash On power up if JP1 is not loaded one of these bitstreams is read by the CPLD and used to program the FPGA The bitstream that is used is determined by a non volatile register called the Boot Section Select BSS register If the BSS register points to a section that does not contain a valid bitstream the Error LED LD...

Страница 14: ...point for project development 4 2 QDRII SRAM Three Cypress CY7C25652KV18 Quad Data Rate II QDRII SRAMs are provided for applications that require high speed low latency memory Each component provides a 36 bit wide data bus and has a density of 72 Megabits Common applications include FIFO buffers and look up tables The notion of Quad data rate comes from the ability to simultaneously read from a un...

Страница 15: ... Please refer to Xilinx Answer Record AR 53364 AR 44587 and UG769 7 Series FPGAs Transceivers Wizard v2 6 User Guide for more information 5 4 PCI Express The NetFPGA SUME is designed with a PCI Express form factor to support interconnection with common processor motherboards Eight of the FPGA s high speed serial GTX transceivers are dedicated to implementing eight lanes of Gen 3 0 8 GB s PCIe comm...

Страница 16: ... Clk0 generated by an any frequency precision clock multiplier jitter attenuator IC20 SI5324 Under most cases when SFP interfaces are configured to be 10Gb Ethernet ports the output clock frequency of SI5324 is set to be 156 25MHz Please refer to reference design in NetFPGA SUME repository for recommended configuration values The transceivers for both SATA connectors Lane 0 1 Bank 116 run from a 1...

Страница 17: ...oard includes a VITA 57 compatible FMC FPGA Mezzanine Card carrier connector A High Pin Count HPC connector is used to provide the maximum possible compatibility with a variety of commercially available mezzanine cards Select I O ports on the XC7V690T are connected to all of the standard Low Pin Count LPC signals on the connector due to the limitations of the FFG1761 package All the I O ports conn...

Страница 18: ...e used for basic user I O These can be useful for debugging designs The pushbuttons are connected to the FPGA via series resistors to prevent damage from inadvertent short circuits a short circuit could occur if an FPGA pin assigned to a pushbutton or slide switch was inadvertently defined as an output The two pushbuttons are momentary switches that normally generate a low output when they are at ...

Страница 19: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Digilent 410 301P KIT 410 301 ...

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