NetFPGA-1G-CML™ Board Reference Manual
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buffering and table lookup. Each 36Kb BRAM can be partitioned into two completely independent 18Kb RAMs to
help facilitate more efficient hardware utilization. Furthermore, each BRAM can be configured for dual-port
operation and includes register infrastructure tp support FIFO functionality. These BRAM ports can be organized in
either single or dual-clock configurations. The Xilinx tool chain includes a rich selection of resources for on-chip
BRAM configuration and initialization. Further information is provided in the Xilinx
7-Series FPGAs Memory
Resources User Guide
(UG473).
5
DDR3 Memory
The NetFPGA-1G includes a Micron MT41K512M8 512 MB DDR3 SDRAM which employs an 800 MHz byte-wide
data bus capable of operating at a data rate of 1600 MT/s. Project development with the SDRAM involves using
the Xilinx Memory Interface Generator (MIG) in either the XPS design tool or the Vivado Design Suite. The MIG is
an interface generation wizard for selecting part types and configuring FPGA Select I/O resources for the memory
hardware interface. The interface is automatically configured by the MIG for use with the AXI4 system bus and
provides options for 2:1 or 4:1 memory-to-bus clock ratios. The NetFPGA-1G uses a VCC
AUX-IO
of 2.0V to support
high performance DDR3 frequency settings. Please see the Xilinx
7 Series FPGAs Memory Interface Solutions User
Guide
(UG586) and the Micron
4Gb:x4,x8,x16 DDR3L SDRAM
data sheet for more details.
6
QDRII+ Memory
A 4.5 MB Cypress CY7C2263KV18 QDRII+ Quad Data Rate SRAM is provided for applications that require high
speed, low-latency memory. Common applications include FIFO buffers and table lookups. The notion of "Quad"
data rate comes from the ability to simultaneously read from a unidirectional read port and write to a
unidirectional write port on both clock edges. The NetFPGA-1G QDRII+ is capable of operating at up to 450MHz to
yield data transfer rates of up to 900 MT/s per 2-byte port. This yields a peak bandwidth of up to 3.6 GB/s. The
Xilinx Memory Interface Generator (MIG) is able to generate and configure an AXI4 based interface into the QDRII+
via the user friendly wizard tool. More information regarding the QDRII+ memory part and the Xilinx MIG tool can
be found in the Cypress
CY7C2263KV18/CY7C2265KV18 data sheet
, the Cypress Application Note
QDR-II, QDR-II+,
DDR-II, DDR-II+ Design Guide
(AN4065), and the Xilinx
7 Series FPGAs Memory Interface Solutions User Guide
(UG586).
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BPI Flash Memory
A 1-Gbit Numonyx BPI (Byte Peripheral Interface) flash memory in a 128 MB x16 configuration is provided to
support high-speed FPGA configuration after board reset. High-speed single-step configuration enables
enumeration via the PCIe interface within 100 mS, as required by the PCI specification. In BPI configuration mode,
the FPGA acts as the bus master, driving the flash address and control signals to transfer previously stored
bitstream data into the configuration SRAM.
The BPI flash has enough capacity to store multiple device configurations. This facilitates multi-stage configuration
boot as well as applications that utilize dynamic reconfiguration. Configuration bitstreams are not the only data
which can be stored in the BPI flash. After configuration is complete, the BPI programming pins may be used as
normal Select I/O within the design. As a result, non-volatile data of any type can also be stored to and retrieved
from the BPI after device configuration is complete. More information regarding BPI based device configuration is